Anwesa Roy
Member level 2
Cant this vhdl program be viewed in simulation?
We are trying to use floating point numbers in our code(to represent real numbers). The code is synthesised properly. However when we try to simulate, error is shown that: compile step failed with errors. The question is cant we view the signal example in the simulation window(Isnt simulation of code possible if we use floating point numbers in vhdl code)?How can we view the simulation for this code?
The idea is taken from the site given below:
https://vhdlguru.blogspot.in/2010/03/fixed-point-operations-in-vhdl-tutorial.html
The code is given below:
We are trying to use floating point numbers in our code(to represent real numbers). The code is synthesised properly. However when we try to simulate, error is shown that: compile step failed with errors. The question is cant we view the signal example in the simulation window(Isnt simulation of code possible if we use floating point numbers in vhdl code)?How can we view the simulation for this code?
The idea is taken from the site given below:
https://vhdlguru.blogspot.in/2010/03/fixed-point-operations-in-vhdl-tutorial.html
The code is given below:
Code:
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-- Company:
-- Engineer:
--
-- Create Date: 08/01/2016 03:49:02 PM
-- Design Name:
-- Module Name: fixed_point1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
entity fixed_point1 is
Port ( a,b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (0 downto 0));
end fixed_point1;
architecture Behavioral of fixed_point1 is
signal example : ufixed (3 downto -4);
begin
example <= "10011100";
end Behavioral;