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Re: Setting an initial condition for VCO simulations in Spec
u can set initial condition inside the inductor or capicator which is making ur resonance circuit model...when u initialize into your schematics.
u can also do this goto Analog Design Environment of Cadence. Select Simulation->Convergence aids->Initial Condition
hopefully i will work
But a single pulse current generator will be trigger for the vco. For instance if you connect a pulse current generator without period and very short pulse after a certain time ( for intance 10ns ) this generator will wake-up the circuit. If you have double crossed vco, you may also use time shifted current pulse generators to wake up the transistors with a time delay.
There are many possibilites to wake up the circuit.
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