Resource and execution time estimation without FPGA board

Hello.

I design, compile and make testbenchs to my VHDL project without using Quartus (I use a script that runs ModelSim command lines), so I don't use analysis or synthesis.

I don't know if it is that simple, but how can I estimate the resource usage for a design? It is kinda big, with 1000 or so lines, uses fixed-point arithmetics, many mathematics and other stuff.

Also, can I estimate the speed (in clock cycles, or maybe even time) that the design would execute, without actually running it? For example, for a 1 MHz clock, it would execute in [x] minutes.

If it matters, it's a project to process video and extract some features from the frames (calculate numbers, basically).

Thanks.

You should be able to estimate resource usage from your architectural diagram and documentation from before you coded (You did these didnt you?) usually you should have a rough idea of multipliers and memories required before you even code anything. Logic is much harder to estimate without synthesising the design.

As for speed, the only way to get this is through quartus and timing analysis. But you can get the number of clock cycles in the pipeline from your testbench in modelsim (data in -> data out - count the clocks). But your circuit doesnt "execute" - it is not a software program. It is a digital circuit. As you're processing video, are you not running the design at the pixel clock or some multiple of the pixel clock? surely you knew what your requirements were for throughput and frame rate before you started coding?

TrickyDicky said:

You should be able to estimate resource usage from your architectural diagram and documentation from before you coded (You did these didnt you?) usually you should have a rough idea of multipliers and memories required before you even code anything. Logic is much harder to estimate without synthesising the design.

As for speed, the only way to get this is through quartus and timing analysis. But you can get the number of clock cycles in the pipeline from your testbench in modelsim (data in -> data out - count the clocks). But your circuit doesnt "execute" - it is not a software program. It is a digital circuit. As you're processing video, are you not running the design at the pixel clock or some multiple of the pixel clock? surely you knew what your requirements were for throughput and frame rate before you started coding?

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Hi, thanks for the answer.

Yes, I planned the implementation in the form of RTL diagrams before I started coding. I have some estimation on resources in the form of recquired memory bits for video frame storage and fixed-point numbers. But I don't know exactly how to estimate logic elements (also, I am not that experienced), without compiling. I'm asking because I'm currently having some trouble compiling my code in Quartus (the last try it ran for more than 24 hours, finally exiting with an error).

I will check this clock counter on ModelSim. I say that my circuit "execute" because I run testbenches in which I put as data in a video or some frames (in the form of text) and got some numbers as data out; I call this process the execution.

Sure, I got the input data in the pixel clock (for example, it is ~75 MHz for basic HDMI), but the calculations don't need to follow that.

As of the requirements of frame rate, it is one of the objectives of the process to discover it. I want to check if the code can be executed in real time, for example, or up to what screen resolution it can process in real time.

marcelos said:

I'm asking because I'm currently having some trouble compiling my code in Quartus (the last try it ran for more than 24 hours, finally exiting with an error).

Click to expand...

This likely means you've written very poor code that is pretty much not synthesizable. I would suspect that you've written the code as a "program" in VHDL software. This typically results in very poor results and extremely long synthesis run times.

marcelos said:

As of the requirements of frame rate, it is one of the objectives of the process to discover it. I want to check if the code can be executed in real time, for example, or up to what screen resolution it can process in real time.

Click to expand...

This seems like you are saying you didn't pipeline the design, otherwise the throughput would likely have been the same as some exact multiple of the pixel rate (depending on how many pixels are processed simultaneously). As you can't seem to just count the number of clock it takes to perform the processing...you probably didn't pipeline the design or write the VHDL as a hardware description.

You probably have badly written arrays that are getting synthesized to FFs as you didn't implement RAM to hold them, etc.