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Configuration memory readback

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nidhints

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How can we readback the configuration memory of a Xilinx FPGA ( Spartan 6) for Single Event Upset Detection and mitigation, which mode of operation would be better? and how the interfacing will be??
 
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Hi,

The configuration is in an external SPI memory with SPI interface.

You may access the configuration either "through" the FPGA. To enable this you first need to write the code into it.

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Otherwise you have to disconnect the memory from the FPGA somehow (analog MUX, socket...) and read it out with external hardware.

Klaus
 

Klaus that's not what the OP was asking...

OP use the Xilinx SEM controller. You will need a extra external SPI flash device if you want more than SECDED. Control is managed by a UART interface.
 

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