Integrating custom coprocessor with ZYNQ

I have finally managed to make a custom IP for the Full-Search Motion Estimation Algorithm. Now that I've tested it and verified that it works, I want to move with the next step, interface it in some way with the ARM processor in the ZYNQ SoC.

So I have some questions regarding both the architectural and the technical procedures needed. Firstly, some details about my design:

The FSME co-processor is being fed with 128-bit data directly from memory and sends back the result (11-bit data) to the CPU. It also needs 3 more signals: clock, reset and start in order to begin the procedure.



So, I believe that the way to go is by implementing some sort of DMA, but I'm completely unaware on how to do that in the ZYNQ context. Also how would it be possible to send data directly to the processor, bypassing the RAM?

I have followed some tutorials regarding the implementation of a custom IP and its integration with ZYNQ PS, but they referred to GPIO like LED blinkers etc. (http://svenand.blogdrive.com/archive/176.html). The procedure in my case should be the same in general? Any tutorials explaining it in more depth?

Thank you in advance for your time and your answers.

Look into the various axi interfaces that you can use for this purpose.

I've already studied some of the various interfaces I can use. However, I don't know how to implement them. For example, I came up with the following block design:



however, I have many scratch-heads. As you can see I've already packaged my IP, but the only ports that are available are the AXI bus, clock and reset. How am I supposed to connect it to DMA IP and also to the rest of the signals?

Look for some example documentation on the subject of the DMA controller.

You also should be able to memory-map the OCM (On-Chip-Memory). You can also have AXI BRAM, but this is lower performance as the CPU must use the AXI GP master ports instead of the AXI HP slave ports. You can get the HP slaves to work with BRAM in theory, but I don't think there are cores for this and you don't want to work with the full AXI interface if there is an easier solution.

http://www.xilinx.com/support/answers/57550.html -- shows 4 example dma designs. The FFT one might be close to what you want. It might be that you want your IP to be the DMA AXI-Lite Master, or that you might want your IP to monitor/arbitrate that feature -- this is the command port. Some of this would be driven by how easy it is to get software support for this feature.

For testing, and low-performace IO, you can actually use some of the low speed peripherals, like GPIO.

edit -- the output of your block would need to be axi4-s for data at a minimum. You might also need axi4 for the control, but I'm not sure. I haven't done much with ZYNQs.