Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

FPGA with SDRAM clk speed

Status
Not open for further replies.
S

sherif123

Member level 3
Joined
Nov 8, 2006
Messages
64
Helped
7
Reputation
14
Reaction score
7
Trophy points
1,288
Activity points
1,804
I have SDRAM that can work using 143MHz frequency.
The SDRAM is connected to an FPGA.
Can I operate the SDRAM with lower clock, like 100MHZ? This is because the FPGA cores can work up to 100MHZ.
I don't want to use dual clock fifos now. I just want to know if it is safe to run the SDRAM with a lower frequency.

Thanks
 

Look at the datasheet for the SDRAM to make sure the specific device you have will support a lower clock frequency many parts did. The other thing to watch out for is to ensure you don't violate the refresh interval when you lower the clock frequency.
 
In contrast to DDR RAM, SDRAM don't use internal PLL and can work at arbitrary low frequencies, with the restrictions of still implementing the required refresh timing. There are also maximum delay times (high µs range) between specific command states. But you can run a SDRAM with clock frequencies e.g. down to 10 MHz if appropriate.

I didn't yet come across SDRAMs with lower clock rate restrictions.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top