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spi transfer in xilinx

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twainerm

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I am using quad spi to talk to an external ADC device. I am unable to read data back from ADC. quad spi IP is configured to master.
when I hook up my board to logic analyser, I do some read data but I am not able print it out or use it for any calculation. Also I see that data from ADC on logic analyser is available as the same clock that i send data to ADC.

Here is my code.

Code: 
u8 wr_data[3];
u8 rd_data[3];
ConfigPtr = XSpi_LookupConfig(SpiDeviceID);
Status = XSpi_CfgInitialize(SpiInstancePtr, ConfigPtr,
ConfigPtr->BaseAddress); 
Status = XSpi_SelfTest(SpiInstancePtr);
Status = XSpi_SetOptions(SpiInstancePtr, XSP_MASTER_OPTION | XSP_MANUAL_SSELECT_OPTION);
XSpi_Start(SpiInstancePtr);
XSpi_IntrGlobalDisable(SpiInstancePtr);

wr_data[0] = 0x01;//start bit is lsb
wr_data[1] = 0xA0;// 
wr_data[2] = 0x55;// can be anything. 

XSpi_SetSlaveSelect(SpiInstancePtr, 0x01);
Status = XSpi_Transfer(SpiInstancePtr, wr_data, rd_data, 3);

Now here when i print rd_data, I get zero.

Please can anyone help me understand what the issue is and how to fix it.
Mark
 
Last edited by a moderator:

This looks like C code.

What processor do you use to communicate with the Quad SPI ?
 

yeah, this is c program. I am using xilinx IP and microblaze. I am trying to talk to an external adc. based on my debug, i think there is a problem in xilinx driver as i do see output from adc on scope. but it is all zero when xspi_transfer is called. xspi_Transfer is the driver function provided by xilinx.
 

I am assuming that Xilinx FPGA is the SPI master and the SPI IP is the slave for it. Then again for the ADC interfacing, the SPI IP is the master and the ADC is its slave.
I can only provide some generic debug methods.

Can you poll the status regs of the SPI IP from the FPGA master, i.e. do a read?
Can you write something to the SPI IP from the FPGA master, i.e. do a write?
If the above are yes, plz check if you are correctly configuring the SPI registers.

Also I see that data from ADC on logic analyser is available as the same clock that i send data to ADC.
Click to expand...
Improper configuration of the SPI might be the reason why the ADC data is not reaching the FPGA.

Divide you communication channels and then try to debug.
 

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