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VHDL_structural_modelling

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Vlsi_design_technology

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Dear All,

I was doing half adder and full adder using structural modelling in VHDL. There are following warnings and errors:
(i) Instance is unbound
(ii) Possible simulation mismatch
Due to this, output shows 'U' i.e. initialized.

How can I remove it.

Thanks in advance for your time and consideration.
 

i) You probably didnt include the source code when you compiled it
ii) fix the code.

Without the code, there isnt much we can really comment on. Post the code and the errors.
 

VHDL code:

Code VHDL - [expand]
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library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FA_structural is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           cy : out  STD_LOGIC;
           s : out  STD_LOGIC);
end FA_structural;
architecture Behavioral of FA_structural is
component HA
port (a, b : in std_logic;
      c, s : out std_logic);
        end component;
component or1
port (a, b : in std_logic;
c : out std_logic);
end component;
signal s1, s2, s3 : std_logic;
begin
U1 : HA port map (a => a, b => b, c => s2, s => s1);
U2 : HA port map (a => s1, b => cin, c => s3, s => s);
U3  : or1 port map (a => s2, b => s3, c => cy);
end Behavioral;


Warning after synthesis:
WARNING:Xst:2211 - "C:/Desktop/full_adder/full_s_vhdl/example/sr/tff/dff/pe/hs/type/siso/piso/fa/fa.vhd" line 51: Instantiating black box module <or1>.
WARNING:Xst:2036 - Inserting OBUF on port <cy> driven by black box <or1>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <sum> driven by black box <HA>. Possible simulation mismatch.

Warning after simulation:
WARNING:Simulator:648 - "fa.vhd" Line 49. Instance ha is unbound
WARNING:Simulator:648 - "fa.vhd" Line 50. Instance ha is unbound
WARNING:Simulator:648 - "fa.vhd" Line 51. Instance or1 is unbound

- - - Updated - - -

Dear Sir/Mam,
Please see the vhdl code and warning after synthesis and simulation. I have attached it.

Thank You.
 
Last edited by a moderator:

Im guessing you forgot to include the code for the HA component.
 

As said by TrickyDicky, source files for components ha and or1 not compiled to work library (not included in the simulated project files).
 

As you seem to be a GUI user and a newbie... Add both the or1.vhd and the ha.vhd files to your project with:
"Project->Add Source"

Keep doing that for any other files you need. Missing files in your project should show up with Red X's (I think) if you open up the + signs to the left of the block in the Hierarchy pane.
Capture.JPG
 

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