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[SOLVED] how to read data from a ddr3 sdram?

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hamidkavianathar

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Hi
I want to read data from a ddr3 sdram. I'm using vivado. my memory model
is M471B2873FHS which is not mentioned in the "xilinx memory interface
generator".
what should I do?
thanks.
( I apologize for my bad English ).
 

Get the memory's datasheet select custom memory in Vivado mig and enter the parameters for the memory from the data sheet values.
 
thanks for the your attention.
excuse me, what is the differences among MT8JTF12864HZ-1G6 and MT8JTF12864HZ-1G4 and MT8JSF12864HZ-1G1 ?
thanks.
 

Clearly you did not read the datasheet...

On the front page of the datasheet:
Capture.JPG

As you can see the -1G6 is the fastest speed grade device, etc.
 
thank you for your comment.
I have created a simple project. I have a microblaze processor and a mig 7 and uart. but it doesn't work. I have just written "print("hello");" but I have not received anything from uart port. do you have idea?
thanks.
 

thanks for the comment.
I have worked with microblaze and uart and gpio. but when I connect a memory interface generator ( mig ) to microblaze, it doesn't work anymore.
 

I referenced the two youtube links as the microblaze design uses a DDR3 just like you are.
 
thanks for the comment. I have read data from a sdram in artyboard. but when i want to read data from a sdram on my board, it doesn't return return anything. I have a uart core in my design but when I add a memory controller it doesn't work anymore. is it possible that my have some bugs?
is there any way to test it?
thanks. I apologize for my bad English.

- - - Updated - - -

thanks for the comment. I have read data from a sdram in artyboard. but when i want to read data from a sdram on my board, it doesn't return return anything. I don't know what I should do.
I also have a uart port in my design but when I add a memory controller it doesn't work anymore. is it possible that my board have some bugs?
is there any way to test it?
thanks. I apologize for my bad English.
 

Assuming that you are using the Xilinx MIG core, do you see the signal init_calib_complete signal going HIGH? That would be the 1st step of debug. You can connect it an on-board LED for visual indication.

I had a similar design in which a uB_MCS was connected to a MIG core and an UART. I had connected the init_calib_complete to the uB_MCS reset input. So only after your DDR3 is ready to be W/R you are activating the processor for further use. In my design after init_calib_complete was HIGH, the uB_MCS and UART was printing out "hello world" and then doing further stuff. You may model something similar.

Do not forget to make use of the ILA and VIO cores for further debug (there is a debug section the Xilinx MIG core spec).

btw- This thread is marked SOLVED! Has it been resurrected again?
 
thanks for your attention.
I checked the init_calib_complete signal. unfortunately, It's always low, I searched in the Internet, but I couldn't find a useful solution.
could you tell me what I should do? thanks.
 
Last edited:

I checked the init_calib_complete signal. unfortunately, It's always low, I searched in the Internet, but I couldn't find a useful solution.
Unfortunately you have hit a brick wall then and I can be of little help if init_calib_complete is LOW.

1. Check if you are supplying the proper clock and reset signals to the core. Check in simulation in any of your signals are going 'X'.
2. Compare your design with MIG DDR3 example design and observe the differences.
3. Other than following the debug methodologies given in the Xilinx MIG core spec, you may post your problem with the details in the Xilinx forums. Use the ILA and VIO debug cores to the best.
 
There is a calibration status byte that can be connected to chipscope/vivado debug cores or perhaps some external pins you can connect to a logic analyzer. The codes produced during calibration will tell you where it fails during calibration and by reading the documentation you can narrow down what step is going wrong.

- - - Updated - - -

I see you were using Vivado, so enable the debug interface in the DDR3 core and then add the Vivado debug cores to your design, then you can monitor the calibration steps.
 
Unfortunately you have hit a brick wall then and I can be of little help if init_calib_complete is LOW.

1. Check if you are supplying the proper clock and reset signals to the core. Check in simulation in any of your signals are going 'X'.
2. Compare your design with MIG DDR3 example design and observe the differences.
3. Other than following the debug methodologies given in the Xilinx MIG core spec, you may post your problem with the details in the Xilinx forums. Use the ILA and VIO debug cores to the best.

thanks. I changed the frequencies of my circuit. now the init_calib_complete signal is high. but still I can't read from it and its uart port doesn't work. I can't find the relationship between uart port and memory controller.
 
Last edited:

thank you all. finally I could do a reading and writing to the memory. I am so stupid. my problem was with IO placement.
 

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