[moved] FPGA Timing Constraints

Hi,
I am using Xilinx kc705 board with VIVADO 15.2 for my project and project have several clocks. In report time summary "Total hold slack" doesn't meet the timing requirement. Therefore by means of "contraints wizard" I am trying to enter several constraints parameter.

For input there are clocks having colck period 37 ns, 10 ns, 15 ns .... and I am supposed to provide the value for following input delays parameters:


Similarly for output there are clocks having clock period 37 ns, 6 ns, 10 ns, 7 ns, ... and I am supposed to provide the value for following output delays parameters:

But I don't know which value should I provide to these parameters. Where i can find such values?

Could anybody please help according to this?

Best regards

Re: FPGA Timing Constraints

The input/output delays depended on the interface parts with FPGA.
I believe those parts have datasheet that provide such timing specification.

Re: FPGA Timing Constraints

Hi, I am looking for one reference design and didn't understand contents inside curly bracket {} of XDC file giving the path:


can anybody please expalin?

Re: FPGA Timing Constraints

1. First of all post it in the correct forum (PLD, SPLD, GAL, CPLD, FPGA Design)!

2. There are many {} in the xdc command, which one is needed?

3. Have you referred to the Xilinx Constraints manual, UG903.pdf where most explanations are present?

the stuff inside a {} are collections in Tcl, which is what xdc/sdc is based on. Collections are just containers (lists) of stuff.

The first {} is specifying the clock pin of a specific register in the hierarchy.
The second {} is input to a regular expression that is looking for all the D pins of registers associated with a bus.

This constraint is probably for a cross clock domain register or they have a tighter requirement than the normal period constraint.

Hi,
the register associated with the bus. here

could you please little bit clarify this ?

I think it is usage of regular expressions.
https://en.wikipedia.org/wiki/Regular_expression

https://www.regular-expressions.info/numericranges.html

......core_reset_dly_reg_p_([0-9]|[0-9][0-9])/D}]

Click to expand...

Means the D input pin of the register defined by *core_reset_dly_reg_p_([0-9]|[0-9][0-9])/D
The part marked in BOLD can take a changing numeric value.


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