Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Using Xilinx ISE 14.7, PCIe core implementation problem

Status
Not open for further replies.
M

minho_ha

Junior Member level 3
Joined
Jun 8, 2016
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
263
I use Xilinx ISE 14.7 for PCIe core generation.

I take given PCIe core IP for vertex-6 ML605 board from Xilinx ISE 'CORE generator'.

Then, I got error message as belows

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
ERROR:pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
their packing might not have been completed.

Mapping completed.
See MAP report file "v6_pcie_v1_7_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors : 2
Number of warnings : 0

Process "Map" failed


Is there anyone solving this problem??

I use Xilinx ISE 14.7 and vertex-6 board.

Thanks to read this post. Help me.
 

ERROR:pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
their packing might not have been completed.

--> The Error show what the problem is.

1/ Your design has more IO than that of the device can support.
2/ Logic is larger than device resource.

You can choose a bigger FPGA according to the resource report of your design. Is this just a core generating design ?
 

Yes. this is just the IP core from 'CORE generator'. There is no edition.
 

Are you implementing only the PCIe IP core with nothing on the user design interface side (i.e., TRN, PL, CFG, DRP, and SYS of Fig 2-1 of UG517) of the design? If so that would mean a lot of extra pins that are normally only internal to a design. And a quick look through the subsequent interface sections shows many hundreds of signals on the user side.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top