minho_ha
Junior Member level 3
I use Xilinx ISE 14.7 for PCIe core generation.
I take given PCIe core IP for vertex-6 ML605 board from Xilinx ISE 'CORE generator'.
Then, I got error message as belows
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
ERRORack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
their packing might not have been completed.
Mapping completed.
See MAP report file "v6_pcie_v1_7_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 2
Number of warnings : 0
Process "Map" failed
Is there anyone solving this problem??
I use Xilinx ISE 14.7 and vertex-6 board.
Thanks to read this post. Help me.
I take given PCIe core IP for vertex-6 ML605 board from Xilinx ISE 'CORE generator'.
Then, I got error message as belows
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
ERRORack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
their packing might not have been completed.
Mapping completed.
See MAP report file "v6_pcie_v1_7_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 2
Number of warnings : 0
Process "Map" failed
Is there anyone solving this problem??
I use Xilinx ISE 14.7 and vertex-6 board.
Thanks to read this post. Help me.