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how to instruct vivado not to add I/O Buffers.

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hamidkavianathar

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hi
I have written this code in vivado and I'm using kintex 7 fpga.

Code:
module top(
     input sys_clk,  //(* io_buffer_type = "NONE" *)
    output tx,
    input rx
    );
//(* IOB = "true" *)
(* IOB = "false" *) reg [51:0] count = 0; 
(* IOB = "false" *) reg reset = 0; 

design_1_wrapper microBlaze(.clk(sys_clk),.rst(reset),.uart_rtl_rxd(rx),.uart_rtl_txd(tx));   

always @(posedge sys_clk)
    begin
        count <= count + 1 ;
        if ( count > 52'h3 && count < 52'h00F )
            begin
                reset <= 0;
            end
        else
            begin
                reset <= 1 ;
            end
    end
    
endmodule

I receive this errors:
PHP:
[Synth 8-5535] port <sys_clk> has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Input Buffer:
	Port I of instance clkin1_ibufg(IBUF) in module <design_1_clk_wiz_1_0_clk_wiz>
Other Components:
	Port C of instance reset_reg(FD) in module top
	Port C of instance \count_reg[51] (FD) in module top
	Port C of instance \count_reg[50] (FD) in module top
	Port C of instance \count_reg[49] (FD) in module top
	Port C of instance \count_reg[48] (FD) in module top
	Port C of instance \count_reg[47] (FD) in module top
	Port C of instance \count_reg[46] (FD) in module top
	Port C of instance \count_reg[45] (FD) in module top
	Port C of instance \count_reg[44] (FD) in module top
	Port C of instance \count_reg[43] (FD) in module top
	Port C of instance \count_reg[42] (FD) in module top
	Port C of instance \count_reg[41] (FD) in module top
	Port C of instance \count_reg[40] (FD) in module top
	Port C of instance \count_reg[39] (FD) in module top
	Port C of instance \count_reg[38] (FD) in module top
	Port C of instance \count_reg[37] (FD) in module top
	Port C of instance \count_reg[36] (FD) in module top
	Port C of instance \count_reg[35] (FD) in module top
	Port C of instance \count_reg[34] (FD) in module top
	Port C of instance \count_reg[33] (FD) in module top
	Port C of instance \count_reg[32] (FD) in module top
	Port C of instance \count_reg[31] (FD) in module top
	Port C of instance \count_reg[30] (FD) in module top
	Port C of instance \count_reg[29] (FD) in module top
	Port C of instance \count_reg[28] (FD) in module top
	Port C of instance \count_reg[27] (FD) in module top
	Port C of instance \count_reg[26] (FD) in module top
	Port C of instance \count_reg[25] (FD) in module top
	Port C of instance \count_reg[24] (FD) in module top
	Port C of instance \count_reg[23] (FD) in module top
	Port C of instance \count_reg[22] (FD) in module top
	Port C of instance \count_reg[21] (FD) in module top
	Port C of instance \count_reg[20] (FD) in module top
	Port C of instance \count_reg[19] (FD) in module top
	Port C of instance \count_reg[18] (FD) in module top
	Port C of instance \count_reg[17] (FD) in module top
	Port C of instance \count_reg[16] (FD) in module top
	Port C of instance \count_reg[15] (FD) in module top
	Port C of instance \count_reg[14] (FD) in module top
	Port C of instance \count_reg[13] (FD) in module top
	Port C of instance \count_reg[12] (FD) in module top
	Port C of instance \count_reg[11] (FD) in module top
	Port C of instance \count_reg[10] (FD) in module top
	Port C of instance \count_reg[9] (FD) in module top
	Port C of instance \count_reg[8] (FD) in module top
	Port C of instance \count_reg[7] (FD) in module top
	Port C of instance \count_reg[6] (FD) in module top
	Port C of instance \count_reg[5] (FD) in module top
	Port C of instance \count_reg[4] (FD) in module top
	Port C of instance \count_reg[3] (FD) in module top
	Port C of instance \count_reg[2] (FD) in module top
	Port C of instance \count_reg[1] (FD) in module top
	Port C of instance \count_reg[0] (FD) in module top
what should I do?
thanks.
 

Why did you do something like the following:

(* IOB = "false" *) reg [51:0] count = 0;
(* IOB = "false" *) reg reset = 0;

Just write a normal RTL and let Vivado do the rest.

I see that you are also generating a reset. You can use the board reset input too.

It is normal for the Vivado synth engine to insert buffers on clk nets.
 
Why did you do something like the following:



Just write a normal RTL and let Vivado do the rest.

I see that you are also generating a reset. You can use the board reset input too.

It is normal for the Vivado synth engine to insert buffers on clk nets.

thanks for the reply.
I had tried them before. but I received error. and I don't have any pin on my board for reset.
 

Input Buffer:
Port I of instance clkin1_ibufg(IBUF) in module <design_1_clk_wiz_1_0_clk_wiz>

--> What did you do when instance the microblaze ? Did you add a clock buffer manually ?
or say, what is the code inside design1_wrapper ?
 
thanks you for the reply.
no, I have not added a clock buffer manually.
and this my constraint file.

Code:
set_property PACKAGE_PIN D10 [get_ports rx]
#set_property IOSTANDARD LVCMOS33 [get_ports rx]
set_property PACKAGE_PIN D11 [get_ports tx]
#set_property IOSTANDARD LVCMOS33 [get_ports tx]
#set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
set_property PACKAGE_PIN AA23 [get_ports sys_clk]
#create_clock -period 20.00 -name sys_clk [get_ports sys_clk]
#set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
 

It looks like there is a "Input buffer" inside design_1_wrapper.
Maybe Vivado insert that buffer when you build "design_1_wrapper".
Let remove it in "design_1_buffer" and try to synthesis again. There will be 1 input buffer for both microblaze and count register clock pin.
 
It looks like there is a "Input buffer" inside design_1_wrapper.
Maybe Vivado insert that buffer when you build "design_1_wrapper".
Let remove it in "design_1_buffer" and try to synthesis again. There will be 1 input buffer for both microblaze and count register clock pin.

so, how can I remove it? I tried to remove it by these command "(* io_buffer_type = "NONE" *)" ,... but it failed again.

- - - Updated - - -

I found the solution.
I had made a very very simple mistake.
I had used the wrong clock signal. I can't use input clock when I have digital clock manager in my circuit.
thank you all.
 

Just in case you dont want to have the buffer, let skip the auto insertion from Vivado when building the design_1_wrapper design. Or, you can manually remove the buffer and just connect its input output.
The input buffer will be inserted between IO and input clock pin later on Vivado.
 
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