Xilinx FIFO doesn't work as well.

Hi.

I'm trying to use the Xilinx FIFO as below, but I can't understand why dout is stopping at that point?
The fifo doesn't work anymore at that point .
Does anyone know how to resolve this problem?

I just let you know, aclk, wr_clk are 192Mhz, bclk, rd_clk are 100Mhz.

but I can't understand why dout is stopping at that point?

Click to expand...

Take a look at the almost_empty and empty signals.
I see that near to 4.2ns empty is asserted HIGH. How can you expect valid data to be out when FIFO is empty?

Does anyone know how to resolve this problem?

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Your write clk is almost double that of the read clock, still the empty is being asserted but full is not asserted.
That makes me suspect your design!
Revise your wr_en and rd_en signals.

With the waveform, we can only speculate what might be wrong.
Another advice, read the spec carefully on how to use the FIFO signals.

We see full and empty asserted simultaneously for some time which must never happen. Could the design be overclocked?

dpaul said:

Take a look at the almost_empty and empty signals.
I see that near to 4.2ns empty is asserted HIGH. How can you expect valid data to be out when FIFO is empty?


Your write clk is almost double that of the read clock, still the empty is being asserted but full is not asserted.
That makes me suspect your design!
Revise your wr_en and rd_en signals.

With the waveform, we can only speculate what might be wrong.
Another advice, read the spec carefully on how to use the FIFO signals.

Click to expand...

Your write clk is almost double that of the read clock, still the empty is being asserted but full is not asserted.
That makes me suspect your design!

Should I have to wait until full the fifo?
Is this like queue doesn't it? I mean the write is always write to the fifo. Then at the half speed, I read the data from the fifo.
I can't find any fail. Because the fifo is alwayes written from the input. Then when I want to read the data whenever I can do read. Am I wrong?

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Yea, of course, it can be able to happen to raise the empty flag, but it that moment, even the data is written to fifo.
Then we assume that fifo does not empty. But it shows always empty at 4.2ns as you said.
Am I wrong? There is no reason to have empty flag after 4.2ns.

Also , I just want to know I've revised that signals,but the same wavefom I'v got.

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FvM said:

We see full and empty asserted simultaneously for some time which must never happen. Could the design be overclocked?

Click to expand...

I don't know what am I supposed to do, but as you can see the wave, the empty and full are asserted at the reset time.

Really, it is harder to find examples where the fifo acts as expected. It is almost like you plotted signals from several different fifos, or if the signals were modifies before/after the actual connection to the fifo.

I didn't see two signals that consistently made sense.

vGoodtimes said:

Really, it is harder to find examples where the fifo acts as expected. It is almost like you plotted signals from several different fifos, or if the signals were modifies before/after the actual connection to the fifo.

I didn't see two signals that consistently made sense.

Click to expand...

I agree, there are no signals in the waveforms shown that behave correctly for any version of the Xilinx FIFO. Even the FIFO going into reset looks wrong with the way the flags behave, they shouldn't go high staggered and with such a large delay after reset is applied.

Without the actual code used there is no use in speculating why u24c02 is having problems.