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[SOLVED] SystemVerilog access members of multidimensional array of struct

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logari84

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Hi all,

I will try to explain what my question is. To make it more clear lets make an example. I have the struct:


typedef struct packed{
logic[`PR_ADDRESS_WIDTH-1:0] address;
logic[`ADC_CODE_WIDTH-1:0] adc0_code;
logic[`ADC_CODE_WIDTH-1:0] adc1_code;
logic[`ADC_CODE_WIDTH-1:0] adc2_code;
logic[`ADC_CODE_WIDTH-1:0] adc3_code;
} T_ENCODED_ADDR_ADC;




In one of my modules I use as input an array of T_ENCODED_ADDR_ADC:

input T_ENCODED_ADDR_ADC [`NUM_OF_REGIONS-1:0] data_in;



Then I need to pass each adc_code to a shifting unit, so I have:

shifter32b shifting_unit[0:3][`NUM_OF_REGIONS-1:0](port mapping here)

where in parenthesis I should map the ports.


I need [0:3] shifting units for each REGION because I have 4 adc_codes:

Nth adc0_code -> 0 index of Nth REGION
Nth adc1_code -> 1 index of Nth REGION
Nth adc2_code -> 2 index of Nth REGION
Nth adc3_code -> 3 index of Nth REGION


The question is: How can I easily map only the adc_codes and not the address of T_ENCODED_ADDR_ADC?


Hope my question is clear enough. If not ask anything.
Thank you in advance!
 

Anyway. I was looking for a "smart" fast way. In the end I used generate to make the instances of my module.
 

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