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[SOLVED] Query on if else statement in VHDL

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hobbyiclearner

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Hello there,

I was going through a LCD controller code and have the following query:

As I know the if else statement is a sequential construct and therefore multiple statements in either if / elsif/ else sections of a statement will execute in the order they are written. If so pls. consider the code snippet below (it basically interfaces with the lcd controller and prints '123456789' on the display).


Code: 
 PROCESS(clk)
    VARIABLE char  :  INTEGER RANGE 0 TO 10 := 0;
  BEGIN
    IF(clk'EVENT AND clk = '1') THEN
      IF(lcd_busy = '0' AND lcd_enable = '0') THEN
        lcd_enable <= '1';
        IF(char < 10) THEN
          char := char + 1;
        END IF;
        CASE char IS
          WHEN 1 => lcd_bus <= "1000110001";
          WHEN 2 => lcd_bus <= "1000110010";
          WHEN 3 => lcd_bus <= "1000110011";
          WHEN 4 => lcd_bus <= "1000110100";
          WHEN 5 => lcd_bus <= "1000110101";
          WHEN 6 => lcd_bus <= "1000110110";
          WHEN 7 => lcd_bus <= "1000110111";
          WHEN 8 => lcd_bus <= "1000111000";
          WHEN 9 => lcd_bus <= "1000111001";
          WHEN OTHERS => lcd_enable <= '0';
        END CASE;
      ELSE
        lcd_enable <= '0';
      END IF;
    END IF;
  END PROCESS;

If I have understood the code correctly, this is what it should do:

**Check for rising edge of clk. If it has occurred, checks lcd_busy and lcd_enable status. If lcd is not busy, it enables it.

**Next, it should check for the value of variable char, and if it is less than 10, starts counter and executes it till value of char is 9. Since char is a variable, it stores (or at least should store) its last value ie. 9

**Next, the case statement is executed. Since the value stored in char is 9, the lcd_bus should get only the last case ie
'1000111001' , the character equivalent of numeral 9. Hence the lcd should display only character 9.

When I copy pasted the code in Xilinx and implemented the lcd_controller with lcd_example, entire sequence of numbers was printed on it ie. '123456789'. What could be the reason. Where is my understanding / concept wrong pls.

The code ofr lcd_contoller is here and code for driving it, ie. the source of the above snippet is here.


Thanks for your time.

Hobbyiclearner
 

The char counter doesn't just "start" this isn't a imperative programming language.

The process is only evaluated when the clock edges occur. Therefore the first time the value of char gets updated to 1 and the first lcd output is 1, on the next clock edge the char value gets updated to 2 and the lcd output is 2,...etc.
 
I'd have to check the synthesis results, but I think the char : char + 1; might result in an implementation where the select to the multiplexer is a register (char) followed by an add by 1 before being used to select the mux output. Not an optimal circuit for performance, this is a direct result of using a variable as it is evaluated immediately.
 

I'd have to check the synthesis results, but I think the char : char + 1; might result in an implementation where the select to the multiplexer is a register (char) followed by an add by 1 before being used to select the mux output. Not an optimal circuit for performance, this is a direct result of using a variable as it is evaluated immediately.
Click to expand...
I presume the design will be clocked very slow to comply with LCD timing requirements (e.g. < 2 MHz) so that the additional combinational delays of the "blocking" variable assignments don't actually matter. The present design is more a design idea than a working design, it's e.g. missing any data setup time, also there's no logic to generate lcd_busy. May be the design is working on a hypothetical LCD character display simulation model rather than a real HD44780 controller.

If it's a kind of exercise problem, you should get rid of the char variable and use good VHDL style with signal assignments instead.
 

Well just to inform you, the above code snippet is to test a lcd_controller (links already provided in my first post). I tried out the code on a Spartan 3 development board with 25 MHz clock and it was working. Also if you have any timing aware vhdl code for lcd_controller, pls do share.

Hobbyiclearner
 

hobbyiclearner said:
Well just to inform you, the above code snippet is to test a lcd_controller (links already provided in my first post). I tried out the code on a Spartan 3 development board with 25 MHz clock and it was working. Also if you have any timing aware vhdl code for lcd_controller, pls do share.

Hobbyiclearner
Click to expand...

There is no such thing as "timing aware VHDL code". It's up to the designer (you) to be aware of timing and how to manage register to register delays in a design and write the code accordingly.
 

Well just to inform you, the above code snippet is to test a lcd_controller (links already provided in my first post). I tried out the code on a Spartan 3 development board with 25 MHz clock and it was working.
Click to expand...

I see. The timing required by the LCD hardware controller is generated in the lower design level. You should have mentioned the previous thread in your post. https://www.edaboard.com/threads/355502/

The code will surely achieve timing closure at 25 or 50 MHz, so there's no need to change anything. Using signals instead of variables for state counters would me my general suggestion though.
 

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