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BRAM read delay.............

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BRAM takes one clock cycle for reading data at output port. But in the schematic there is no register was inferred with in the BRAM instant. How that one clock cycle delay happened ?
 

Have looked in depth and have search carefully?
Which FPGA?
Can you mention the spec for that BRAM?

To get an answer you must ask a question with all associate details!

For Xilinx there are 'Core Output Registers' (pg058-blk-mem-gen).pdf just before the BRAM dout pin due to which you get a 1 clk delay.
 

dpaul said:
Have looked in depth and have search carefully?
Which FPGA?
Can you mention the spec for that BRAM?

To get an answer you must ask a question with all associate details!

For Xilinx there are 'Core Output Registers' (pg058-blk-mem-gen).pdf just before the BRAM dout pin due to which you get a 1 clk delay.
Click to expand...

device :vertix7 xc7v2000t
i have open the schematic using .edif and look in for the dout register, that schematic does not have the dout reg. where can i identify this dout reg ?
 

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Click to expand...
In fact we don't know if you see the regular read delay of synchronous BRAM or an additional register delay. You should show a timing diagram, e.g. simulation wave window.
 

The Xilinx BRAM has embedded registers on the Address lines and will always have a one clock cycle delay from applying address-read_enable before the data is output. This address to read data delay is shown in the timing diagrams in the BRAM user guide (have you read that over thoroughly?). These registers do not show up in a schematic because they are built into the BRAM.

See third bullet on page 12: All inputs are registered with the port clock and have a setup-to-clock timing
specification
see 6th bullet on that same page: A read operation requires one clock edge

There are also optional output registers, which I also believe will not show up in a technology schematic if used (I think the restriction is no reset and no enable on the output registers of a BRAM will allow the tools to merge the registers into the BRAM itself).
 
ads-ee said:
The Xilinx BRAM has embedded registers on the Address lines and will always have a one clock cycle delay from applying address-read_enable before the data is output. This address to read data delay is shown in the timing diagrams in the BRAM user guide (have you read that over thoroughly?). These registers do not show up in a schematic because they are built into the BRAM.

See third bullet on page 12: All inputs are registered with the port clock and have a setup-to-clock timing
specification
see 6th bullet on that same page: A read operation requires one clock edge

There are also optional output registers, which I also believe will not show up in a technology schematic if used (I think the restriction is no reset and no enable on the output registers of a BRAM will allow the tools to merge the registers into the BRAM itself).
Click to expand...

See third bullet on page 12: All inputs are registered with the port clock and have a setup-to-clock timing
specification

In that above line "All inputs" means which includes input port, address port, write enable port ,..etc ?
 

In that above line "All inputs" means which includes input port, address port, write enable port ,..etc ?
Click to expand...
Is there any other meaning of "all inputs" that you consider?
 

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