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    Inserting two inverters instead of a buffer in set up optimization

    How does inserting two inverters instead of a buffer fix set up violation?

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    Re: Inserting two inverters instead of a buffer in set up optimization

    To fix setup violation, I suggest that you change from tiny cells to huge cells instead of inserting buffers.

    Buffer or inverter insertion for setup violation may be effective in big transition time.
    (long distance between cell2cell or max capacitances...)

    Still, If you need to insert buffer for fixing setup violation, Buffer insertion may be effective.

    because cell count is less than inserting two inverters.



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    Re: Inserting two inverters instead of a buffer in set up optimization

    Hey biju4u90,

    Yes, inserting two inverters instead of a buffer will fix the set up violation.
    Setup is violated when data path is slow compare to clock path (by slow I mean higher delay in path) that means clock edge is arriving before the data is set to the expected value.
    If data path is too long then transition time of the data will get increase because of the RC value of the path. And when it will reach to the pin, Its transition time will be higher and set up will get violated.

    If you have place one buffer in the long data path then it will reduce the transition time temporarily but eventually when signal will reach to the pin, transition time will get increase and it will lead to the setup violation.
    So instead of using one buffer use two inverters placing apart. It will help reducing the transition time and eventually reduce the total data path delay.

    So when setup is violated because of the higher transition delay, then you can use this method to solve the setup violation.
    Let me know if you need any other information.



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  4. #4
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    Re: Inserting two inverters instead of a buffer in set up optimization

    There are two reasons for delay improvement using inverter;

    1. Compared to Buffer, Inverter cell delay is less [Buffer is noting but back 2 back connected inverter]
    2. And using two inverter, RC delay delay is further divided & improving transition & delay

    ---[BUFFER]------------------------------------------------------------------->|[Load]
    ---[INVERTER]------------------------[INVERTER]--------------------------->|[Load]



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