Rth(junction to PCB) of SMT FET with just three tiny pads?

This IRF6648 FET claims to have Rth(Junction to PCB) of 1 degC/W. (datasheet page 3)
However, page 8 of its datasheet shows that its PCB Pads are just basically three 1mm by 1mm pads.
That surely is too small to allow a thermal resistance from junction to the PCB of just 1 degc/W?


IRF6648 Datasheet:
http://www.irf.ru/pdf/irf6648.pdf

junc to pcb, is just that, thru the pads ONLY, i.e. the thermal drop across the pads, then you need to heatsink the pcb (easy if it is Alumina or Aluminium, not so easy if it is FR4), these devices are designed for top & bottom conduction...

it is still only 12.5 degC/watt even under note 7, (1 cubic inch copper on pcb AND top side small heatsink)

Thanks,
We intend to gap-pad THIS IRF6648 fet to a heatsink which is above the PCB….the application does not allow us to have a heatsink at the back of the PCB.
Its part of a sync buck converter, the inductor of which is going to be dissipating 1.8W in its windings and putting that heat into the PCB……we were hoping that the FETs could transfer the inductor windings heat up from the PCB and to the heetsink, but with the tiny size of those little pads under the fet, I doubt they will transfer much heat through the fet from the pcb to the heetsink?

The Inductor is a IHLP5050CE-01 type, and even though we are gap-padding it to the heetsink above the PCB, I doubt much of the windings heat will be able to transfer that way…..windings heat will conduct into the pcb unfortunately…..the pcb not having a heatsink beneath it, since there’s components there.

Inductor IHLP5050CE-01
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Besure to have adequate exposed copper for acceptable, Rca. and the coil ambient is not room temp but that heatsink rise plus ambient.

The datasheet is not at fault and appears to be well designed to achieve this with a large 2520 conductive internal case footprint to the small pads. Keep in mind the Rca with 1 sq in of double sided copper with Rja= 12,

Otherwise, take Rja-Rjs=45-1=44 'C/W. The case top R will be poor by comparison if connecting to heatsink. Max temp rise of Tj is 10'C for a great design , +20'C rise for adequate and + 40'C rise for a marginal design measured at solder point. Enclosed in case.

Thanks, and even if this type of fet has a larger drain pad (as the linked Si7370), then it doesnt really help if the excess copper pour connected to this land is more than half an inch squared in area (ie little improvement in Rth(JA)....as the 9th page shows...

Flat FET thermal situation
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