ROM and RAM connection

Kosyas41 · Jun 10, 2016

Hello,
Im write top level entity for ROM and RAM blocks,I want to connect ROM block with RAM.In ROM block data_a_i and data_b_q I want to connect with data_a and data_b in RAM block.But I faced with error/Could you pls help me to solve this problem

Code:

library ieee;
     use ieee.std_logic_1164.all;
     use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all ;
    use ieee.math_real.all ;
    use ieee.math_complex.all ;
entity ROMRAM is 
    port (
        CLOC: IN std_logic;
        ADD: IN integer range 0 to 511;
        DATA_WIDTHi : integer := 256;
        ADDR_WIDTHi : integer := 256;
        
        clk    : in  std_logic;    
        we_ai   : in  std_logic;
        addr_ai : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_ai   : out std_logic_vector(DATA_WIDTHi-1 downto 0);
        we_bq   : in  std_logic;
        addr_bq : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_bq    : out std_logic_vector(DATA_WIDTHi-1 downto 0));
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
       data_b_q: OUT integer range 0 to 255
        );
end component;
        
Component dp_ram_rbw_scl is
generic (
        DATA_WIDTH : integer := 256;
        ADDR_WIDTH : integer := 256
            );
    port(
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end component;
for all : sync_rom use entity work.sync_rom(rtl);
for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
Signal     data_a_i: integer range 0 to 255;--interanal signals
Signal     data_b_q: integer range 0 to 255;--interanal signals

begin
-- Component Instantiation
C1: sync_rom Port map ( 
                                clock => CLOC,
                                address =>ADD,
                                data_a_i =>data_a_i,
                                data_b_q =>data_b_q
                                );
C2: dp_ram_rbw_scl Port map (
                                    clk=>CLOC,
                                    we_a=>we_ai,
                                    addr_a=>addr_ai,
                                    data_a =>data_a_i,
                                    q_a=>q_ai,
                                    we_b=>we_bq,
                                    addr_b=>addr_bq,
                                    data_b =>data_b_q,
                                    q_b=>q_bq
                                );
                                data_a<=to_integer(data_a_i);
                                data_b_q<=to_integer(unsigned(data_b));

end rtl;

but i have error

Code:

Error (10476): VHDL error at Vhdl2.vhd(67): type of identifier "data_a_i" does not agree with its usage as "std_logic_vector" type

vGoodtimes · Jun 10, 2016

Signal data_a_i: integer range 0 to 255;--interanal signals
data_a : in std_logic_vector(DATA_WIDTH-1 downto 0) ;

This is the error.

Kosyas41 · Jun 10, 2016

Is it possible to convert it?or I should change the type of data?

Kosyas41 · Jun 10, 2016

Im solved this problem with conversion

Code:

library ieee;
     use ieee.std_logic_1164.all;
     use ieee.numeric_std.all ;

entity ROMRAM is 
generic(        
		  DATA_WIDTHi : integer := 8;
        ADDR_WIDTHi : integer := 8);
    port (
        CLOC: IN std_logic;
        ADD: IN integer range 0 to 511;

		  data_a : in std_logic_vector(DATA_WIDTHi-1 downto 0);
		  data_b : in std_logic_vector(DATA_WIDTHi-1 downto 0);
        data_a_i : in integer range 0 to 255;
		  data_b_q : in integer range 0 to 255;
        --clk    : in  std_logic;    
        we_ai   : in  std_logic;
        addr_ai : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_ai   : out std_logic_vector(DATA_WIDTHi-1 downto 0);
        we_bq   : in  std_logic;
        addr_bq : in  std_logic_vector(ADDR_WIDTHi-1 downto 0);
        q_bq    : out std_logic_vector(DATA_WIDTHi-1 downto 0));
end ROMRAM;
architecture rtl of ROMRAM is
--- Component decalarartion
Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
        data_b_q: OUT integer range 0 to 255
        );
end component;
        
Component dp_ram_rbw_scl is
generic (
        DATA_WIDTH : integer := 8;
        ADDR_WIDTH : integer := 8
            );
    port(
        clk    : in  std_logic;    
        we_a   : in  std_logic;
        addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_a : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_a    : out std_logic_vector(DATA_WIDTH-1 downto 0);
        we_b   : in  std_logic;
        addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0) ;
        data_b : in  std_logic_vector(DATA_WIDTH-1 downto 0) ;
        q_b    : out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end component;
for all : sync_rom use entity work.sync_rom(rtl);
for all : dp_ram_rbw_scl use entity work.dp_ram_rbw_scl(rtl);
Signal     data_a_i_i: integer range 0 to 255;--interanal signals
Signal     data_b_q_i: integer range 0 to 255;--interanal signals

begin
-- Component Instantiation

C1: sync_rom Port map ( 
                                clock => CLOC,
                                address =>ADD,
                                data_a_i =>data_a_i_i,
                                data_b_q =>data_b_q_i
                                );

C2: dp_ram_rbw_scl

Port map (
                                    clk=>CLOC,
                                    we_a=>we_ai,
                                    addr_a=>addr_ai,

                                    data_a =>data_a,
                                    q_a=>q_ai,
                                    we_b=>we_bq,
                                    addr_b=>addr_bq,
                                    data_b =>data_b,
                                    q_b=>q_bq
                                );
											data_a_i_i<= to_integer(unsigned(data_a));
											data_b_q_i<= to_integer(unsigned(data_b));
											data_a_i_i<= data_a;
end rtl;

but now,when I open RTL viewer/I didt see connection between data_a and data_a_i
data_b and data_b_q
Is it correct code?

dpaul · Jun 10, 2016

Chk your port map code area.
Use the same signal name for port mapping.

Kosyas41 · Jun 10, 2016

Yes I checked/whats wrong?Could you pls give me some hint

ads-ee · Jun 10, 2016

The data_a pins of the ROM are outputs, but you are assigning them with the following code:

Code VHDL - [expand]
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data_a_i_i<= to_integer(unsigned(data_a));
data_b_q_i<= to_integer(unsigned(data_b));
data_a_i_i<= data_a; -- why are you assigning this again?

- - - Updated - - -

You will need to convert the other direction from integer to std_logic_vector:

Code VHDL - [expand]
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the_slv <= std_logic_vector(to_unsigned(the_int, the_slv'length));

Kosyas41 · Jun 10, 2016

Thanks,as you said before I should do like this?

Code:

C2: dp_ram_rbw_scl

Port map (
                                    clk=>CLOC,
                                    we_a=>we_ai,
                                    addr_a=>addr_ai,

                                    data_a =>data_a,
                                    q_a=>q_ai,
                                    we_b=>we_bq,
                                    addr_b=>addr_bq,
                                    data_b =>data_b,
                                    q_b=>q_bq
                                );
											data_a_i_i<= to_integer(unsigned(data_a));
											data_b_q_i<= to_integer(unsigned(data_b));
											data_a_i_i <= std_logic_vector(to_unsigned(data_a,data_a_i_i'length));

ads-ee · Jun 10, 2016

No, Outputs must not be on the Left Hand Side (LHS) of a assignment.

data_a_i_i is an output of the ROM

Code VHDL - [expand]
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Component sync_rom is
    port(
        clock: IN std_logic;
        address: IN integer range 0 to 511;
        data_a_i: OUT integer range 0 to 255;
        data_b_q: OUT integer range 0 to 255
        );
end component;
 
C1: sync_rom Port map ( 
                                clock => CLOC,
                                address =>ADD,
                                data_a_i =>data_a_i_i,  -- this is an output DO NOT assign anything to this signal
                                data_b_q =>data_b_q_i
                                );

- - - Updated - - -

It would actually make more sense to use unsigned as the type for data_a_i and data_b_q and perhaps even for address. As you already included the numeric_std library it would then only require a cast to change the type between the two component instances.

Kosyas41 · Jun 10, 2016

Ok, I want to connect data_a and data_a_i
data_b and data_b_q,
and data_a_i_i is like an internal signal.Am I right?
I little bit confused how should I assigned connection between those ports
Im trying to follow this instructions

ads-ee · Jun 10, 2016

You would have saved yourself a bunch of headaches if you had just used the exact same port types on both components instead of mixing two different types.

But as that is what you have....

Code VHDL - [expand]
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--From integer to slv:
component blah
...
integer_output : out integer range 0 to 255;
...
);
 
component blah_blah
...
slv_input : in std_logic_vector (7 downto 0);
...
);
 
-- component interconnection signals
signal slv_sig : std_logic_vector(7 downto 0);
signal int_sig : integer range 0 to 255;
 
--port map of blah
integer_output => int_sig, -- int_sig is driven by the blah component
--port map of blah_blah
slv_input => slv_sig,
 
-- convert integer to slv
slv_sig <= std_logic_vector(to_unsigned(int_sig, slv_sig'length));

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ROM and RAM connection

Kosyas41

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