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[SOLVED] Source-synchronous data output (Spartan-6)

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hornysquid

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Hello, I'm trying to implement source-synchronous output from Spartan-6. So I use a constraint to place output data registers into IOBs, and clock goes through ODDR2. So now clock and data switch almost simultaneously, but the downstream device requires a hold time of 1ns, how can I achieve that? Or I shouldn't use IOBs for data output, but then I won't be able to control the skew of the data? Thanks
 

One option is to use a phase shifted version of the clock coming from a DCM.
A second option is to use the IODELAY2 to phase shift all the data outputs by more than the 1 ns. See I/O Delay Overview starting at page 70 in the Spartan-6 FPGA SelectIO Resources document.
 
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