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Video distribution networks. Video sent as UDP packets over Ethernet are based on a 125 MHz clock. They are received by a Ethernet MAC and the MPEG Transport Stream (MTS) payload is extracted. The payload was encoded based on a 27 MHz clock, which has a count value embedded in packets within the MTS. This count value is extracted to ensure the TS is output at the correct rate.
As you can see there are at a minimum two clock domains in this design one that is based off the 125 MHz clock for the Ethernet and one clock domain that has to be at 27 MHz for the MTS video to work.
In practice there are actually far more clock domains for something like this to be implemented.
In general, there are a multitude of reasons for multiple clocks and or clock frequencies in electronic design. In the above example, 125 MHz for Ethernet is used as the PLL/PISO multiplier in the PMA of the PHY. There are clock crossing domains. Typically when you transmit in serial (Ethernet/PCIe/etc) you have a slower frequency (125 MHz) for Parallel data realm, which is subsequently spun up via PLL and DLL to a line rate frequency for serial transport, then spun back down through a SIPO to a parallel frequency. It really depends on bandwidth, protocol requirements, power, capability etc.
As you can see there are at a minimum two clock domains in this design one that is based off the 125 MHz clock for the Ethernet and one clock domain that has to be at 27 MHz for the MTS video to work.
Hello,
I was thinking of clock like DS1307 for calendar.
but as you said the working is quite difficult understand.
Thanks for giving explanation i have seen crystal clock in embedded at 20Mhz or less
but when i open some circuit there is very high crystal frequency to operate circuits.
Hello,
I was thinking of clock like DS1307 for calendar.
but as you said the working is quite difficult understand.
Thanks for giving explanation i have seen crystal clock in embedded at 20Mhz or less
but when i open some circuit there is very high crystal frequency to operate circuits.
This is because ... they need to be quicker or so.
There is no rule to have a fixed frequency in every design. And also, there is no rule to use 1 clock frequency in one design.
Depend on the need of data rate, performance speed, you can have other than one frequency in one design. This is very obvious in this world.
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