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VHDL newbie - VHDL construct question

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arve9066

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Hi

I am using the CESYS EFM 02 board for getting started with FPGA development with VHDL. I had a doubt on one of the constructs used on the example codes given in their website. 

Code VHDL - [expand]
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subtype RNG_SLAVE_SELECT is natural range 30 downto 28;
To_Integer(unsigned(master.adr(RNG_SLAVE_SELECT)))

If the master.adr is a 32 bit vector std_logic_vector(31 downto 0), what does the line no 2 actually do?

As I said before, I am pretty new to VHDL, So pardon me if this is 'duh' question
 
Last edited by a moderator:

Strange.

If master.adr is a std_logic_vector, then master.adr(rng_slave_select) selects a single +bit of that slv. It is then converted to unsigned and then converted to an integer. And that integer will be either 1 or 0.

Maybe I'm reading this wrong, but it doesn't make a lot of sense to me...
 

arve9066 said:
Hi

I am using the CESYS EFM 02 board for getting started with FPGA development with VHDL. I had a doubt on one of the constructs used on the example codes given in their website.

1. subtype RNG_SLAVE_SELECT is natural range 30 downto 28;
2. To_Integer(unsigned(master.adr(RNG_SLAVE_SELECT)))

If the master.adr is a 32 bit vector std_logic_vector(31 downto 0), what does the line no 2 actually do?

As I said before, I am pretty new to VHDL, So pardon me if this is 'duh' question
Click to expand...

- To_integer() takes as input an unsigned vector of any length up to 32 bits and converts it to an integer
- unsigned() takes as input a std_logic_vector and converts it to unsigned
- master.adr(RNG_SLAVE_SELECT) slices out the 'RNG_SLAVE_SELECT' bits from master.adr and creates a std_logic_vector. Since RNG_SLAVE_SELECT is defined to be a range of 30 downto 28, then master.adr(RNG_SLAVE_SELECT) is the same thing as the three bits master.adr(30 downto 28).

Putting that all together, bits 30 downto 28 of master.addr are interpreted as unsigned 3 bit vector and then converted to an integer so the end result will be an integer in the range 000 to 111 (binary) or 0 to 7 (decimal).

Kevin Jennings
 
Master.adr (rng_slave_select) selects a single bit, not 3 bits. It's no different than master.adr (28) or master.adr (30).
 

VHDL has an odd construct here. It allows a subtype to be used as a range index. This differs from a signal of that subtype -- this is the subtype name itself.

eg, this isn't indexing as normal where you have signalName(integerValue). this is signalName(subtypeName). It actually does select three bits.


This means you do not need to do:
Code: 
constant x : std_logic_vector(30 downto 28) := (others => '0');

y(x'range);
 
Code VHDL - [expand]
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constant MCB_BASEADR : std_logic_vector((ADR_WIDTH-1) downto 0) := x"0000_0000";
  constant BRAM_BASEADR : std_logic_vector((ADR_WIDTH-1) downto 0) := x"1000_0000";
  constant CFG_FLASH_BASEADR : std_logic_vector((ADR_WIDTH-1) downto 0) := x"2000_0000";
  constant GPIO_BASEADR : std_logic_vector((ADR_WIDTH-1) downto 0) := x"4000_0000";
  constant UART_BASEADR : std_logic_vector((ADR_WIDTH-1) downto 0) := x"5000_0000";
 
  constant SL_MCB_ID : natural := To_Integer(unsigned(MCB_BASEADR(RNG_SLAVE_SELECT)));
  constant SL_BRAM_ID : natural := To_Integer(unsigned(BRAM_BASEADR(RNG_SLAVE_SELECT)));
  constant SL_CFG_FLASH_ID : natural := To_Integer(unsigned(CFG_FLASH_BASEADR(RNG_SLAVE_SELECT)));
  constant SL_GPIO_ID : natural := To_Integer(unsigned(GPIO_BASEADR(RNG_SLAVE_SELECT)));
  constant SL_UART_ID : natural := To_Integer(unsigned(UART_BASEADR(RNG_SLAVE_SELECT)));
 
   subtype RNG_SLAVE_SELECT is natural range 30 downto 28



This is the construct used by them.. So this defines the different IDS as constants essentially. So

constant SL_MCB_ID is 0
constant SL_BRAM_ID is 2
constant SL_CFG_FLASH_ID is 4
constant SL_GPIO_ID is 0 again
constant SL_UART_ID is 2 again

I am not understanding why they would then decode it in such a way that the IDs are not unique..
 
Last edited by a moderator:

arve9066 said:
This is the construct used by them.. So this defines the different IDS as constants essentially. So

constant SL_MCB_ID is 0
constant SL_BRAM_ID is 2
constant SL_CFG_FLASH_ID is 4
constant SL_GPIO_ID is 0 again
constant SL_UART_ID is 2 again

I am not understanding why they would then decode it in such a way that the IDs are not unique..
Click to expand...

You didn't decode correctly. Bits 30 downto 28 are not the three most significant bits, they are the least three significant bits of the upper nibble. So SL_MCB_ID decodes to 0; SL_BRAM_ID decodes to 1; CFG_FLASH_BASEADR decodes to 2, etc.

Kevin Jennings
 
Last edited by a moderator:

Yeah.. I realized it a little later after I posted.. Anyways..
 

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