anilineda
Member level 3
I am working on a academic project in which FPGA vc707 acts as a ENDPOINT (flashed a axi4 system bit file on it)and installed on a PC motherboard which acts as a host with a linux OS.
basic question is,1. why the address spacing is different for both devices? what one should do to make it same.
2. fpga works at 150 Mhz . but cpu is having 2ghz. how frequency mismatch is handled here? is it really a plays a role here?
3. for a 32 bit data bus, axi 4 will get 218 pins (including all 5 channels) that connects to axi2pcie core block and just 64 pins comes out of that core . how this 218 (memRead,memWrite commands) turning down to just 64 pins(i.e x4 lane)(pcie TX,RX TLP packets) ? provide resource for this question.
thanks.
basic question is,1. why the address spacing is different for both devices? what one should do to make it same.
2. fpga works at 150 Mhz . but cpu is having 2ghz. how frequency mismatch is handled here? is it really a plays a role here?
3. for a 32 bit data bus, axi 4 will get 218 pins (including all 5 channels) that connects to axi2pcie core block and just 64 pins comes out of that core . how this 218 (memRead,memWrite commands) turning down to just 64 pins(i.e x4 lane)(pcie TX,RX TLP packets) ? provide resource for this question.
thanks.
