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Hi,
IP wonder what the range ordering means. What problems could I encounter if I have :
Code: 
signal my_signal : std_logic_vector (3 downto 0);
then
Code: 
my_signal(0 to 1) <= "11";
Thank you for the explanation.
 

I am not proficient with VHDL, so to be on the safe side I always use downto to keep a clear distinction of MSB and LSB.

For example,

signal t1 : std_logic_vector(7 downto 0); --7th bit is MSB and 0th bit is LSB here.

and,

signal t2 : std_logic_vector(0 to 7); --0th bit is MSB and 7th bit is LSB here.

You are free to use both types of representations, just have to make sure that other parts of the design are written accordingly.
 
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Code: 
signal a : std_logic_vector(3 downto 0); -- common use case
signal b : std_logic_vector(0 to 3); -- vhdl default for slv
signal c : std_logic_vector(1 to 4); -- vhdl default for some other types
signal d : std_logic_vector(7 downto 4);

a <= "1101";  -- a(3) = '1'; a(2) = '1'; a(1) = '0'; a(0) = '1';
b <= a; -- b(0) = a(3); b(1) = a(2); b(2) = a(1); b(3) = a(0);  b = "1101";
c <= b; -- c(1) = b(0); c(2) = b(1); c(3) = b(2); c(4) = b(3);  c = "1101";
d <= c; -- d(7) = c(1); d(6) = c(2); d(5) = c(3); d(4) = c(4);  d = "1101";

a(1 downto 0) <= b(0 to 1);  -- a(1) = b(0); a(0) = b(1);  a = "1111"
a(0 to 1) <= "11";  -- error, a is defined as "downto"
a(4) <= '1'; -- error, no bit 4.
 

Code: 
signal b : std_logic_vector(0 to 3); -- vhdl default for slv
signal c : std_logic_vector(1 to 4); -- vhdl default for some other types

What do you mean by VHDL default? There's no default direction in ieee.std_1164 library, see the definition of std_logic_vector:
Code: 
TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

The correct point is that arrays with different range direction aren't assignment compatible.
 

If you have "11001010" as a literal, this will be a std_logic_vector(0 to 7).
VHDL string literals, like "hello" are string(1 to 5) as the range is positive typed.

specifically, if you have an unconstrained vector as an input to a function:
Code: 
function badLsb(x : std_logic_vector) return std_logic is
begin
  return x(0);
end function;

-- badLsb("10000") will return '1', as bit index 0 is the leftmost bit for a literal.
-- badLsb(c) will be an error.  c being std_logic_vector(1 to 4)
 
Last edited:
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    FvM

    FvM

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I agree that a default direction and range must be assumed by the compiler in your example.

But which IEEE 1076 clause specifies it?
 

Interesting. I'm not actually sure. This was mostly from the issues I had with unconstrained vectors in the past. At one company, it was even common to have unconstrained ports.

IMO, outside of functions, unconstrained vectors are bad practice:
* The default direction is either "to" or "idk"
* It is easy to get (x to y) or (x downto y), where neither x nor y is zero.
* output ports that are unconstrained vectors must be connected. (the arch could call out the attributes)

This is almost certainly confusing to the OP. I doubt they were aware of unconstrained vectors at all, let alone that they might be actually useful and horrifying.
 

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