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Quartus schematic errors

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AndrewBB

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Hi all, I've just tried for the very first time to use a CPLD and am having problems with transfering a schematic to the CPLD.

Can anyone explain the errors on the pinouts

Code dot - [expand]
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Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (10034): Output port "D0" at test.v(36) has no driver
Warning (10034): Output port "D1" at test.v(37) has no driver
Warning (10034): Output port "D2" at test.v(38) has no driver
Warning (10034): Output port "D3" at test.v(39) has no driver
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "D0" is stuck at GND
Warning (13410): Pin "D1" is stuck at GND
Warning (13410): Pin "D2" is stuck at GND
Warning (13410): Pin "D3" is stuck at GND
Warning (21074): Design contains 5 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "CLK"
Warning (15610): No output dependent on input pin "CLR"
Warning (15610): No output dependent on input pin "DATA"
Warning (15610): No output dependent on input pin "LATCH"
Warning (15610): No output dependent on input pin "SEL"
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (169140): Reserve pin assignment ignored because of existing pin with name "CLK"
Warning (169140): Reserve pin assignment ignored because of existing pin with name "CLR"
Warning (169140): Reserve pin assignment ignored because of existing pin with name "D0"
Warning (169140): Reserve pin assignment ignored because of existing pin with name "D1"
Warning (169140): Reserve pin assignment ignored because of existing pin with name "D2"
Warning (169140): Reserve pin assignment ignored because of existing pin with name "D3"
Warning (169140): Reserve pin assignment ignored because of existing pin with name "DATA"
Warning (169140): Reserve pin assignment ignored because of existing pin with name "LATCH"
Warning (169140): Reserve pin assignment ignored because of existing pin with name "SEL"


Thanks
 
Last edited by a moderator:

Think about this...how is someone supposed to explain your problems if we don't have the test.v source. It's pretty obvious that is the source of the problem and not the output of a transcript/log window is only reporting the problems in that code.
 
Ah Yes..

Code Verilog - [expand]
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module test
(
// {ALTERA_ARGS_BEGIN} DO NOT REMOVE THIS LINE!
 
    CLK,
    CLR,
    D0,
    D1,
    D2,
    D3,
    DATA,
    LATCH,
    SEL
// {ALTERA_ARGS_END} DO NOT REMOVE THIS LINE!
 
);
 
// {ALTERA_IO_BEGIN} DO NOT REMOVE THIS LINE!
input           CLK;
input           CLR;
output          D0;
output          D1;
output          D2;
output          D3;
input           DATA;
input           LATCH;
input           SEL;
 
// {ALTERA_IO_END} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_BEGIN} DO NOT REMOVE THIS LINE!
// {ALTERA_MODULE_END} DO NOT REMOVE THIS LINE!
endmodule


test.png
 
Last edited by a moderator:

your test.v file is empty, are you sure you've compiled the schematic correctly? Personally I've never used the schematic entry tools of Quartus, so I'm not sure how the schematic gets converted to something synthesizable, but it's pretty obvious that some step was left out as your test.v file has nothing in it.

- - - Updated - - -

Did you follow the tutorial on schematic entry? **broken link removed**

Seems like you might have skipped the stuff in Section 6 on page 19 "Compiling the Designed Circuit".
 

Thats whta I was thinking It only has the pinouts.

I had only started with the schematic and thats what compiled from it.

I followed a Youtube example.

I have no experiance of VDHL or Verilog hence me going the Schematic route.

I just chose the compile icon and thats what it produced.

Any suggestions or procedure would be great.
 

AndrewBB said:
Any suggestions or procedure would be great.
Click to expand...

Just drop something in your schematic, anything, in between an input and an output. see if the verilog generated is populated with something. then take it from there.
 

I have a circuit as shown on the third post of this thread. For some reason the inputs and outputs are registered but not the muxes registers and counters.
I'm using the Lite version of the software.

Not sure what else to do.

Maybe this is a bug
 

well your counter's clock input is connected to CLR and not a clock that input is also connected to the GN pin of two of the muxes. The muxes themselves don't have clocks. The select is also screwy in this design as the final mux only selects the A inputs as it has a hard ground symbol attached to it.

I'm wondering how much digital design experience you have. I presume not too much given the state of this design. I'm not even sure of the intent of this design as the counter does nothing (the outputs aren't even attached to anything).
 

AndrewBB said:
I have a circuit as shown on the third post of this thread. For some reason the inputs and outputs are registered but not the muxes registers and counters.
I'm using the Lite version of the software.

Not sure what else to do.

Maybe this is a bug
Click to expand...

just AND two inputs and connect to an output. generate the verilog. should work.
 

ads-ee said:
well your counter's clock input is connected to CLR and not a clock that input is also connected to the GN pin of two of the muxes. The muxes themselves don't have clocks. The select is also screwy in this design as the final mux only selects the A inputs as it has a hard ground symbol attached to it.

I'm wondering how much digital design experience you have. I presume not too much given the state of this design. I'm not even sure of the intent of this design as the counter does nothing (the outputs aren't even attached to anything).
Click to expand...


I think maybe your not understanding the circuit.
Maybe I have more experience in TTL than you think.
Just because an input says CLK does not mean it has to have a clock input!
This has been breadboarded using real IC's and working.

It's a real circuit being transferred onto CPLD.

The problem I have is with the Quartus Lite software and making this circuit work.
 

Well multiple decades worth of designs that work in VHDL/Verilog/TTL/SSI/MSI. I still don't see what this design is supposed to do, I think it's drawn incorrectly.

Sure you can use a clock input without a clock, but that doesn't change the fact that there IS no clock inputs on those muxes, therefore you won't have an flip-flops (registered) outputs from them.

Use VHDL/Verilog and forget the schematic.
 

Your correct that the counter is not connected. My error.

circuit 2.PNG

Ive renamed the inputs and outputs due to the compiler auto configuring them to the CPLDs internal clk etc.

It's now compiling 0 errors and 4 warnings.
 

Don't get why you would use a counter as the LSB is only equivalent to a toggle FF. Most of the "counter" will be removed from the design as it's not used...leaving a toggle FF.
 

ads-ee said:
Don't get why you would use a counter as the LSB is only equivalent to a toggle FF. Most of the "counter" will be removed from the design as it's not used...leaving a toggle FF.
Click to expand...

Not the full circuit so I may be using the rest of the counter.
But this section works independently hence why I used it to test out the CPLD.
It's not a complex circuit.
12bit serial into 2 nibble or 4 nibble read.
The fourth nibble read is wasteful as the last nibble as a mode marker.
Sorry you could not understand it.
Maybe you over estimate what you know.
I was only trying to get some help regarding the Altera Quantus software thanks for trying.
 

AndrewBB said:
Not the full circuit so I may be using the rest of the counter.
Click to expand...
FYI, we can only go by what you post, and then have to guess the rest.

Sorry you could not understand it.
Maybe you over estimate what you know.
Click to expand...
wow now this is plan rude. Originally I was unsure of your level of expertise. I was thinking you might be a junior engineer, hence my comment about the design, as it appears to be random connections with no decrenable function. It was also 'broken' I.e. drawn wrong. So am I expected to know that was an unintentional mistake on your part? Based on this comment I suppose you expect an expert to know exactly what you left out with no context?

Besides I'm not drawing schematics, I code this stuff in VHDL or Verilog and have worked on a number of first pass success ASIC designs, in architecture design, coding, and verification. So yes I do know my stuff.
 

I tried to understand the error in the schematic design shown in post #3 but couldn't reproduce it. One possible explanation is that the warning list has been produced with a different design.

The warnings seem to belong to a typical "null" design where no output depends on an input so that the design completely removed during synthesis. But that's not the case with the post #3 schematic, even it may seem useless or it's purpose isn't clear. I see has only one output stuck to ground.

The discrepancy between the design and the compilation report confuses the discussion.
 

ads-ee said:
FYI, we can only go by what you post, and then have to guess the rest.

wow now this is plan rude. Originally I was unsure of your level of expertise. I was thinking you might be a junior engineer, hence my comment about the design, as it appears to be random connections with no decrenable function. It was also 'broken' I.e. drawn wrong. So am I expected to know that was an unintentional mistake on your part? Based on this comment I suppose you expect an expert to know exactly what you left out with no context?

Besides I'm not drawing schematics, I code this stuff in VHDL or Verilog and have worked on a number of first pass success ASIC designs, in architecture design, coding, and verification. So yes I do know my stuff.
Click to expand...

So what you are saying is real designers don't do schematic design anymore? Shocking. What year is this, 1979? What is this VHDL you speak of?

:)
 

ThisIsNotSam said:
So what you are saying is real designers don't do schematic design anymore? Shocking. What year is this, 1979? What is this VHDL you speak of?
:)
Click to expand...

Funny, but I'm sure you can find someone on the forum that is convinced they are just as productive using a library of 7400 based schematic components to produce a 1 M gate ASIC or FPGA design. :)


Seriously I do find the Block design stuff like in Vivado and Quartus works nicely if you are building a processor-centric system or a processing system using streaming interfaces, but it usually ends up with one not understanding the protocols between blocks and not understanding what is wrong when things don't work as you expect. It's one of the reasons I read the bus specs (AXI4 or Avalon) before having used those tools the first time.

- - - Updated - - -

I still think the OP should have just coded this in Verilog (or VHDL) it's not that hard to pick up.
 

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