ROM and FFT relation

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
	 use STD.textio.all;
    ENTITY sync_rom IS
     PORT (
      clock: IN std_logic;
      address: IN integer range 0 to 511;
      sample_i: OUT integer range 0 to 255;
	   sample_q: OUT integer range 0 to 255	
     );
    END sync_rom;
    ARCHITECTURE rtl OF sync_rom IS
    BEGIN
    PROCESS (clock)
     BEGIN
     IF rising_edge (clock) THEN
      CASE address IS
       WHEN 0 => 
		    sample_i <= 128;
		    sample_q <= 128;
       WHEN 16 => 
			 sample_i <= 128;
			 sample_q <= 128;
		 WHEN 70 =>
			 sample_i <= 128;
			 sample_q <= 128;      
		 WHEN 400 => 
			 sample_i <= 128;
			 sample_q <= 128;
       WHEN OTHERS  => 
		 	 sample_i <= 0;
			 sample_q <= 0;
		
      END CASE;
     END IF;
     END PROCESS;

END rtl;