Dissipationdue to reverse recovery in sync FET of sync buck?

We are using the IRF6648 FET as a sync FET in a sync buck with vin=28v vout=1.5v, iout=17.1A, fsw=200khz.

The Qrr for IRF6648 is 56nC.
Therefore the dissipation in the lower FET due to this Qrr is ......
(Qrr * Vin * Fsw)/2

Thus equals 0.155W

However, the datasheet conditions for Qrr measurement involved a di/dt of 100A/us.

In our sync Buck converter the di/dt would be about 17.1A/8ns which equals 2137A/us.
Given this difference, how much more would the FET dissipation be due to this reverse recovery?

IRF6648 FET datasheet
https://www.infineon.com/dgdl/irf6648pbf.pdf?fileId=5546d462533600a4015355ec6e561a59

PS: There's little point in using a schottky in parallel with the sync fet because sufficiently voltage derated schottkys for such purpose have high vf and would not sufficiently stop the intrinsic fet diode from conducting.
-The intrisic fet diode would still conduct very significantly even with a paralleled schottky.

The following article, in the “conclusion” on page A-32 states that a higher di/dt (in the sync fet's diode at turn-on of top fet) actually reduces overall turn-on switching losses….Page A-30 details the reasons why….
Switching losses in MOSFETs:
https://www.fairchildsemi.com/techn...covery-and-Its-Effect-on-Switching-Losses.pdf

..this is quite interesting, because for example in Boost PFC stages in CCM, its well known that if using ultra-fast diodes for the boost diode, then it is crucial to reduce the di/dt in the diode at FET_turn-on (by slowing up the FET turn-on by using a high value series gate resistor) in order to reduce the losses in the FET due to the reverse recovering diode. So why the above article comes up with a different conclusion is interesting. Violent Reverse recovery in boost pfc diodes by having too high di/dt in the diode is known to be a “killer” for the boost PFC converter.

So what do you make of our 2000+A/us di/dt and the resultant losses in the top fet and in the sync fet?

If the sync rect FET is up to the job, properly sized and
phased, it ought to prevent the body diode from ever
going forward-biased. Why is it driven into body diode
conduction? Fix that if you can. But if you're only trying
to estimate the loss, be sure first that it is in play.

The dead time between sync fet and top fet turning on means the diode conducts.

Sure, if there's dead time enough. When I was designing
POL integrated bucks, we tried to control the timing such
that the sync rect turned on right about when the output
reached 0, and before it went more than a couple of
hundred mV negative. There's a sweet spot for efficiency
between too positive (hard switching) and too negative
(reverse recovery and temporary high I*V). Whether it
can be held, well, ... depends on what you have access
to.