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Pure Combinational ALU (Tasks : Add,Mul and Sub)

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Morell

Morell

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Hi everyone

I need help with writhing this combinational ALU

Here is my code 

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity PocketCalculator is
     Generic (Bits : integer := 8);
     
    Port ( Input_1 : in  STD_LOGIC_VECTOR (Bits-1 downto 0):=(Others =>'0');
           Input_2 : in  STD_LOGIC_VECTOR (Bits-1 downto 0):=(Others =>'0');
              Select_Operator : in STD_LOGIC_VECTOR (2 downto 0):=(Others =>'0');
           Output : out  STD_LOGIC_VECTOR (Bits-1 downto 0):=(Others =>'0'));
end PocketCalculator;
 
architecture Behavioral of PocketCalculator is
    
begin
 
    Process(Input_1,Input_2,Select_Operator)
    Begin
    
        Case Select_Operator is 
        
            When "100" =>   
                Output <=  Input_1 +  Input_2;
                                
            When "010" =>
                -- Right here I have to do the multiply part, 
                -- and I dont know what to write here
                
            When "001" =>
                Output <= Input_1 + not Input_2 + 1;
                
            When Others => 
                NULL;
        End Case;
    End Process;
    
end Behavioral;



and here are my problems

1- I want to add two 8-bit inputs (input_1 and Input_2) WITH CARRY!!!
so Output should be a 9-bit signal or port.
but when I define Output as a 9-bit port, a warining comes up in synthesize
and an error comes up during simulating with ISIM (The simulator is stopped)

So what should I do to add two 8-bits and put it in a 9-bit signal or port?

2- My secend problem is with multiplying part.
I want to use the Output port right here but it should be 16-bit port.
first : i dont know the code or function that does this on std_logic_vector
secend : if I define output as a 16-bit port, I will be facing some other problems with adding part


Please help me, I am really confused

- - - Updated - - -

Hi Guys

I wrote a new code and it seems to work correctly

what do you think about this one
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;

entity PocketCalculator is
	 Generic (Bits : integer := 8);
	 
    Port ( Input_1 : in  STD_LOGIC_VECTOR (Bits-1 downto 0):=(Others =>'0');
           Input_2 : in  STD_LOGIC_VECTOR (Bits-1 downto 0):=(Others =>'0');
			  Select_Operator : in STD_LOGIC_VECTOR (2 downto 0):=(Others => '0');
           Output : out  STD_LOGIC_VECTOR ((2*Bits)-1 downto 0):=(Others =>'0'));
end PocketCalculator;

architecture Behavioral of PocketCalculator is
	Signal Add_Result,Sub_Result : Std_logic_vector (Bits downto 0):= (Others=>'0');
	Signal Mul_Result : Std_logic_vector ((2*Bits)-1 downto 0):= (Others=>'0');
begin

			
	Add_Result <= ('0' & Input_1) + ('0' & Input_2);			
	Sub_Result <= ('0' & Input_1) + (not ('0' & Input_2)) + 1;
	Mul_Result <= Input_1 * Input_2;
				
	Output <= "0000000" & Add_Result when Select_Operator="100" else
	               std_logic_vector(resize(Signed(Sub_Result),16)) when Select_Operator="010" else
		       Mul_Result when Select_Operator="001" else 
		       (Others =>'0');

end Behavioral;
 

It probably works, but is horrible and ugly.

1. You've included non-standard std_logic_unsigned library. Dont. Use the numeric_std library properly
2. Why are inputs and outputs std_logic_vector? why not just used signed or unsigned?
3. Why does it have to be combinatorial? this will get you poor timing results.
 
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    Morell

    Morell

    Points: 2
    Helpful Answer Positive Rating
1- Re:
I dont know anything about these librarys, I just saw an example and put that there.
right now, if i remove std_logic_unsigned, does it work? if it doesn't, what is your suggestion

2- Re:
Again, Examples,
If I use signed or unsigned instead of Std_logic_vector, does it work correctly on the board?
What about overflow bit for adder?

3- Re:
This is an exercise that my teacher gave me. and he said "The design should be PURELY COMBINATIONAL".


Tnx alot
 

The logic that this should generate isn't that bad. Without knowing the desired clock rate, it is hard to know if there will be any performance issues. It looks like an 8x8 multiply and a mux for the longest path.

my concerns:
1.) Select_Operator isn't indented consistently. (you have mixed tabs/spaces in your editor)
2.) you have magic numbers for each operation.
3.) you really should be using "unsigned", at least within the module.
4.) you resize to 16 bit, and you prepend 7 bits. "Bits" is now a generic that must be 8.
5.) Even without using unsigned types, you can use x - y. std_logic_unsigned defines that, it just doesn't define x + (-y).
6.) I actually couldn't find operator precedence rules for when-else. This might be a reason to use ("000" & x) when y else ....
7.) Bits is an integer. it should be natural with a range, or positive. For example, Bits = -100 is a valid choice.
8.) people will complain if you use std_logic_unsigned because
 
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    Morell

    Morell

    Points: 2
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-- I agree with TrickyDicky that you should use the library "numeric_std". I really recommend it after several years in work.
-- You should define whether your mathematics are for signed or unsigned data types. Conversion to/from signed/unsigned from/to std_logic_vector is easy.
-- Function "resize" will help you instead of using " ('0' & Input_1)".
-- Different output sizes for addition and multiplication should not an issue. Your ALU block should have fixed size. You should assume that even if you are multiplying two numbers, each 16 bits, the output value should be small enough to be in 16 bits too. This may seem strange but if you have experience in programming, C for example, you may define three integer data types You can multiply two of them and store the result in the third variable.
 
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    Morell

    Morell

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