UART 16550 in Vivado

Hello All,

I am using Zynq 7000 SOC in my design. I have enabled UART 0 and UART1 in the PS with extra modem signals. In addition to this, I need to create 2 more UARTs on the PL side for which I have chosen UART 16550 IP core. All 4 UARTS are 4 wired. ie they include TX, RX, RTS and CTS signals. I don't need the other signals which vivado automatically gives like DCDN, Rin etc. Few signals which are of input type, I connected them to a constant 0. However the signals of the UART which are of output type cannot be connected to any constant. When implement the design and open it, the tool asks me to assign pins to these extra signals as well which is not desired in my project. How do i remove these extra redundant signals of the UART? I tried to edit the UART HDL file as well but its a read only file. Please suggest

Regards

However the signals of the UART which are of output type cannot be connected to any constant.

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Why can't you leave them o/p signals unconnected in the RTL during the module's inst in a top-level wrapper?
VHDL: signal_name <= open;
Verilog: .signal_name();

When implement the design and open it, the tool asks me to assign pins to these extra signals as well which is not desired in my project.

Click to expand...

Assign them to the unused FPGA pins to get around the error.

Thanks a lot DPaul. I assigned the ports which I didn't require as open in the top level wrapper file. When I did this and then ran synthesis, the vivado threw an error. I have attached a snapshot of the error. My command within the portmap of the top level wrapper file is as mentioned below.

UART_0_dcdn => open

Error is mentioned in the link below

https://obrazki.elektroda.pl/3784522300_1464757828.png

Please tell me what to do

Hi,

Maybe because DCD is an input....

Klaus

The discussion sounds confused. A HDL tool will never generate errors for unconnected outputs. The error "has no actual or default value" will be only given for unconnected input ports that don't assign a default value in the component.

Maybe because DCD is an input....

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Should be in fact expected because it is with original 16550 as well. DTR and RTS are the only handshake outputs, all other are inputs and should be connected to constant level if unused.

Hi,

Is it a good idea to create our own wrapper file according to which inputs I require. There is a possibility of letting vivado manage the wrapper file. However, I think it would be a good idea to create a second wrapper file on top of the 1st one according to which inputs and outputs which I require. Please tell me if this would be a good idea

Create your own if it has MEANINGFUL IMPACT.

There is a possibility of letting vivado manage the wrapper file.

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It is advisable to do stuff either manually or using TCL scripting.