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How STA becomes complicated if latch is inferred?

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biju4u90

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In many articles, I have seen that latch inference has to be avoided because it makes STA complicated. How STA becomes complicated if a latch is inferred in my design instead of an FF?
 

I can answer your question from an FPGA design standpoint.
FPGAs don't have inbuilt latches - Only FFs.
If you describe a latch in HDL, the synthesis tool will try to make do and emulate a latch behavior via a combinatorial loop (using the LUTs of the fabric).
Although in simulation you'll see the latch reacting in zero time - the real behavior of the circuit will have timing characteristics that are hard to predict and may vary strongly with temperature change.

But as I said, this is for FPGAs.
Hope someone can illuminate us more.
 

That is a good explanation in FPGA point of view. But what happens in the case of ASIC? Will the ASIC tool infer latch using combinational loops itself? Or do the ASIC libraries have in built latch cells available? Can anyone who has good knwoledge in ASIC please help?

- - - Updated - - -

shaiko said:
Although in simulation you'll see the latch reacting in zero time - the real behavior of the circuit will have timing characteristics that are hard to predict and may vary strongly with temperature change.
Click to expand...

But if it is the scenario, how can we do STA on any path? Because any R2R path consists of combinational logic in between and temperature will effect them also!!
Is it like, when we feedback the output of the combinational loop to its input, output may toggle between '1' and '0' multiple times because latch is level triggered??
 

This is what I think:
Timing driven place and route is designed to work well with synchronous logic.
If you pipeline a path (using DFF), the synthesis tool will consider the timing budget between register A and B.
A latch (despite being a storage element) is treated as any other combinational circuit that "eats away" your timing budget - it will drop your reported Fmax.
 

biju4u90 said:
In many articles, I have seen that latch inference has to be avoided because it makes STA complicated. How STA becomes complicated if a latch is inferred in my design instead of an FF?
Click to expand...

Not sure I agree. Latches should be avoided because it usually means poorly described logic. That would be, IMO, the #1 reason to avoid latches.

Now, back to the question, std cell libraries usually have a variety of latches and you can design using them if you want. Here is an article that does a reasonable comparison between flops versus latches. https://www.eetimes.com/document.asp?doc_id=1278980
 

Cannot directly answer your question as I have never done STA on a latch based design.
In ASIC designing, within the design team, if you give a synth. design containing latches (which is not intended) the DfT engineer should be shouting back at you!
Better to fix such issues at the design stage and then go for STA and other ASIC design flows.

Read the 3rd part of this article for an overview on STA for latches:
https://www.eetimes.com/document.asp?doc_id=1278980
 

there is something to be said about useful skew. it is analogous to borrowing that we get from latch based design, but using flip flops. modern CTS performs skew balancing at the same time as datapaths are optimized for better results. in the past the goal of CTS used to be zero skew, now it is to get the most useful skew.

now the question becomes: what is harder from an EDA point of view? latch borrowing or skew optimization? I do not know the answer.
 

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