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  1. #1
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    can we use latch to build a counter?

    i have an idea, i want to build a counter with cmos latch(two inverter back-to-back connected), not with D flip--flop, may i?

    but i got the bad results, it did not work.

    can anyone give me some advice? can this be realizable?

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  2. #2
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    Re: can we use latch to build a counter?

    There are special design methodologies for sequential asynchronous circuits. Following these methods, it can be possible.

    You only mentioned a bare idea instead of giving a logic circuit. Thus we can't see how your design fails.



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  3. #3
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    Re: can we use latch to build a counter?

    Quote Originally Posted by FvM View Post
    There are special design methodologies for sequential asynchronous circuits. Following these methods, it can be possible.

    You only mentioned a bare idea instead of giving a logic circuit. Thus we can't see how your design fails.
    in D-flip-flop method, div-by-2 circuit is built easily, that is the basic cll of a counter, but with cmos latch method, because it is level-sensitive, not edge-sensitive, so, div-by-2 circuit is difficult to build using only cmos latch(two inverter back-to-back, only half of a D-flip-flop).

    is there some way to build a div-by-2 circuit using only cmos latch?
    thanks.



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