preethi19
Full Member level 5
Hi i am working with D-flip flop with 2 inputs and outputs in vivado. I ran the timing analysis with the following delay for the inputs and output
input (CLK)-> period =10ns, rise at=5ns, fall at=10ns
input (D) = 3ns delay
output (Q) = 1ns delay
output (Qbar) =1ns delay
When i run the behaviour simulation logic is correct. But with these constraints if i run the "post synthesis timing simulation" i get the following.
Can anyone pls tell me why is the output Q is not getting into logic 1 after a delay... from 0 to 105ns the logic for both Q and Qbar is not turning out correct. After like 105 ns then the logic seems to be working wer Qbar becomes logic 1 after a delay a bit more than 3ns. Pls see the attached image which has the schematic, the paths for setup analysis.
Der are 4 paths but i have attached only path 2 and 3 since they both describe about Qbar. So if you see path 3 first which is from (D to the D reg)... So here the arrival time is mentioned to be 8 something ns. But this is for D and not for Qbar. Now seeing path 2 we can see that the final data arrives at Qbar at 10 something ns. So if you see the simulated fig. Shouldnt my Qbar become high at 101ns???? becoz thats the time when the data arrives at Qbar and not at 108ns. Can someone pls tell me wer i am going wrong with this... Thank you!!!
input (CLK)-> period =10ns, rise at=5ns, fall at=10ns
input (D) = 3ns delay
output (Q) = 1ns delay
output (Qbar) =1ns delay
When i run the behaviour simulation logic is correct. But with these constraints if i run the "post synthesis timing simulation" i get the following.
Can anyone pls tell me why is the output Q is not getting into logic 1 after a delay... from 0 to 105ns the logic for both Q and Qbar is not turning out correct. After like 105 ns then the logic seems to be working wer Qbar becomes logic 1 after a delay a bit more than 3ns. Pls see the attached image which has the schematic, the paths for setup analysis.
Der are 4 paths but i have attached only path 2 and 3 since they both describe about Qbar. So if you see path 3 first which is from (D to the D reg)... So here the arrival time is mentioned to be 8 something ns. But this is for D and not for Qbar. Now seeing path 2 we can see that the final data arrives at Qbar at 10 something ns. So if you see the simulated fig. Shouldnt my Qbar become high at 101ns???? becoz thats the time when the data arrives at Qbar and not at 108ns. Can someone pls tell me wer i am going wrong with this... Thank you!!!