d-flip flop- post synthesis timing simulation

Hi i am working with D-flip flop with 2 inputs and outputs in vivado. I ran the timing analysis with the following delay for the inputs and output

input (CLK)-> period =10ns, rise at=5ns, fall at=10ns
input (D) = 3ns delay
output (Q) = 1ns delay
output (Qbar) =1ns delay

When i run the behaviour simulation logic is correct. But with these constraints if i run the "post synthesis timing simulation" i get the following.

Can anyone pls tell me why is the output Q is not getting into logic 1 after a delay... from 0 to 105ns the logic for both Q and Qbar is not turning out correct. After like 105 ns then the logic seems to be working wer Qbar becomes logic 1 after a delay a bit more than 3ns. Pls see the attached image which has the schematic, the paths for setup analysis.

Der are 4 paths but i have attached only path 2 and 3 since they both describe about Qbar. So if you see path 3 first which is from (D to the D reg)... So here the arrival time is mentioned to be 8 something ns. But this is for D and not for Qbar. Now seeing path 2 we can see that the final data arrives at Qbar at 10 something ns. So if you see the simulated fig. Shouldnt my Qbar become high at 101ns???? becoz thats the time when the data arrives at Qbar and not at 108ns. Can someone pls tell me wer i am going wrong with this... Thank you!!!

My guess is some mismatch somewhere, and that there is a 100ns reset. The simulation waveform is consistent with a 100ns reset time, even if the schematic is not. Perhaps the simulation and schematic differ?

Thank you for the reply!!! But der is not "reset" input at all. Plus i wrote the vhdl code and elaborated the design and then wrote a test bench checked the behaviour verification (with no constraints set). No errors nothing. So wer can i find the mismatch mentioned?? Can u pls tell me that. after verifying i synthesized the design, set constraints and then i had to resynthesize since it told me modifications are made and need to do it once more. And then i ran the "post-synthesis simulation". The schematic is always the same and only wen delay is added the simulation varies. But shouldn't the simulation differ since now constraints are added in the design. Can u kindly let me know if i am missing out any step or am i doing any step wrong...

Without seeing the netlist and/or the simulation testbench we can only guess.

You mention in your first post that you did a behavioral simulation of the VHDL. Are you using the same testbench for both the behavioral and netlist simulation?

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Also are you sure that there isn't a GSR in the simulation models of the primitives that is taking effect?

That is my best guess given the circumstances.

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Try applying your D input sequence after say 150 ns