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DC-AC Converter (Push-Pull) Testing

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james81

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Hi Guys

So I have just built this inverter but I have an issue trying to get it to work..

Firstly all parts appear to be working fine independently, and with H-Bridge disconnected I get a pretty stable 340v DC from the rectifier.
I also get SPWM from the H-Bridge using a 12v supply.

But, when the 340v dc is connected with the H-bridge, the rectifier voltage drops to around 40v dc at the rectifier and I get 18v AC rms at the H-Bridge output.
This tested without load connected and before the LC Filter stage, which I haven't got to yet.

Any ideas why this is happening?


*So far I have destroyed my rectifier -

I was thinking my problem may be because the inductor needs minimum load, for continuous current mode.

And, as I had a current limiting resistor in place between the source and ground of the Half-bridge mosfets, I decided to remove that first.
(This was initially in place to prevent any damage to the circuit as I wasn't sure how the circuit would behave)

I replaced the resistance with a 3 amp fuse as this would be enough to allow CCM on the primary whilst protecting the mosfets in case something goes wrong.
(The mosfets can handle around 16 amps)

School boy error though, should have disconnected the rectifier, blew two of the diodes, and now waiting for new diodes.

In hindsight i'm a bit annoyed at myself as I hastily used a standard BS-1362 plug top fuse, and probably not wise for 12v supply.
I think this might have caused a voltage spike on the primary, exceeding 600v rating of the diode - although if this is the case i'm not sure if I could blame the fuse?

Until I get new diodes I am at a lose end trying to think of reasons why the primary side voltage drops so abruptly when the H-bridge is connected.

If anyone is able to give some guidance, Id appreciated the help.

There is another issue regarding the SG3525, I have the frequency set using the components as shown on the diagram - this does not produce the calculated 188 kHz though, it give me the 100kHz I require, not quite sure why that's happening?

Thanks
James
 

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That is a bad circuit with no big C after L1, if the H bridge devices are conducting and then switch off there will be a fet killing spike, also explains your losses....
 
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    james81

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O well.. back to the drawing board.. do you have any advice for calculating this capacitor?
 

I wonder what's the purpose of L1 at all?

Another likely problem is overvoltage in transformer push-pull stage caused by leakage inductance. Will need snubbers or clamping circuit, in any case it results in poor efficiency.

Finally I'm not sure if you achieve sufficient H-bridge dead time with transistor logic circuit formed by Q2 to Q5. Could result in shoot-trough.
 
I'm loosely following another design on the net which doesn't explain the purpose of anything, just calculations really.
Haven't really considered if L1 is mandatory to be fair, assumed was to reduce ripple current after rectification.

Leakage inductance is new to me, and definitely something i'l have to research.

I have a fuse protecting the h-bridge, thinking this would blow if shoot through occurred?

I'm starting to think this project is getting a C at best now.. unless i manage to sort it out within 2 weeks.
Looks like it was probably a mistake for taking this on in year 2 :(
 

at 50 or 100kHz the transformer design and construction are quite critical...

- - - Updated - - -

p.s. for 100kHz on the control chip the osc needs to run at 200kHz, 50kHz power circuit a better idea...
 
at 50 or 100kHz the transformer design and construction are quite critical...

- - - Updated - - -

I spent alot of time researching the transformer to make sure was designed correctly, selecting the correct core, considering skin effect etc.

Im pretty sure its fine for 100Khz and 200W

p.s. for 100kHz on the control chip the osc needs to run at 200kHz, 50kHz power circuit a better idea...

I considered 50kHz but the output inductor and capacitor size doubled so went for 100kHz in the end.

Looking into this further, I now seems obvious that I need an RCD snubber and large capacitance (bulk capacitor?) after L1 but these seem complicated to calculate.

Would I be correct in saying I need to work out the leakage inductance and parasitic capacitance of the transformer/rectifier to calculate the RC of the snubber?

As for the bulk capacitor, im really not sure how to calculate this..
 

The peak input power of a sine inverter is double the average power, this suggests to make the bus capacitor large enough to smooth the DC bus current and make the DC/DC converter run at almost constant power with respectively higher efficiency (several 100 µF to 1000 µF) . If L1 still makes sense is up to a calculation. I guess it can be omitted without much negative impact.

The primary drain overvoltage can be best clamped with a RCD snubber, as used in flyback converters. Of course a topology with energy recovery would be preferred, but it's not possible for simple transformer push-pull.

As a minor point, R11 resistance seems an order of magnitude too low, power disspation is very high with intended 340 V bus voltage.

A fuse will be never fast enough to protect against shoot-trough.
 

The peak input power of a sine inverter is double the average power, this suggests to make the bus capacitor large enough to smooth the DC bus current and make the DC/DC converter run at almost constant power with respectively higher efficiency (several 100 µF to 1000 µF) . If L1 still makes sense is up to a calculation. I guess it can be omitted without much negative impact.

The primary drain overvoltage can be best clamped with a RCD snubber, as used in flyback converters. Of course a topology with energy recovery would be preferred, but it's not possible for simple transformer push-pull.

As a minor point, R11 resistance seems an order of magnitude too low, power disspation is very high with intended 340 V bus voltage.

A fuse will be never fast enough to protect against shoot-trough.

Thanks for the advice, the figures you have giving for the DC bus capacitor are helpful, I will try to find some sources for calculation.
Could you advise if this should this be a polarized electrolytic and/or would ESR and Ripple current be a factor to consider carefully?

I will check out Flyback RCD snubbers to see If I can calculate this, although dont I need to somehow measure the transformers leakage inductance and parasitic capacitance for these calcs?

In hindsight the fuse point that seems obvious now - thankfully the fets didnt get damaged.
I have the deadtime set to 300ns, but I will adjust to its maximum 1.5us for further test to be on the safe side.

I'm really glad for the help, this was to much of a task for my limited knowledge.
I don't plan too have this powering anything - I'l just be glad to get a sine wave out of the other end now.

Hopefully that enough to get me decent pass mark for the project.
 

I wonder what's the purpose of L1 at all?
Agree, its a very unfortunate choice of circuit.

It looks to me like a very poor attempt at building a classic current driven inverter, which would work, but requires two very strict operating conditions.
There must always a load on the output, and the drive to the output bridge must be overlapping, such that there is no dead time. The bridge must directly short out top to bottom during each switching cycle to maintain the current flow through L1.
Any overlap or momentary zero conduction condition will be instant death due to extreme flyback voltage, as there is no voltage clamping anywhere.

Current driven inverters are very good for some highly specialised applications such driving motors and highly capacitive loads. But are totally useless as a general purpose inverter, as the inverter must always be run loaded.
 
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given that the control chip cannot generate overlapping gate drive, it is more likely the o/p C has been left off the schematic...
 
Agree, its a very unfortunate choice of circuit.

It looks to me like a very poor attempt at building a classic current driven inverter, which would work, but requires two very strict operating conditions.
There must always a load on the output, and the drive to the output bridge must be overlapping, such that there is no dead time. The bridge must directly short out top to bottom during each switching cycle to maintain the current flow through L1.
Any overlap or momentary zero conduction condition will be instant death due to extreme flyback voltage, as there is no voltage clamping anywhere.

Current driven inverters are very good for some highly specialised applications such driving motors and highly capacitive loads. But are totally useless as a general purpose inverter, as the inverter must always be run loaded.

Ok I take your points, Im out of my depth here,
I will connect load in future but there is deadtime and cant change that,
Voltage clamping is my inexperience, hopefully i will learn from this..

- - - Updated - - -

The whole thing is a dog's breakfast, and a very unfortunate choice.

Yeh I totally agree its no master piece, but im also no engineer, did 14 months at college to date. I will have to persevere, cant turn back now unfortunately..

I think the bus capacitor and snubber suggestions have been helpful, and will keep some load connected in future also.
Will just have to wait and see what happens after this I suppose.

Thanks
 

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