preethi19
Full Member level 5
Hi i am working with Vivado and so far i am only familiar with writing a verilog code and its test bench and verifying its behavioral functionality. I am trying to learn about timing analysis and theoretically i am familiar with concepts of static timing analysis of setup and hold violations. I would like to check this with my design. I don't have a kit and some sites i found that we need to have the pins assigned to have a XDC file. I have no clue. Is der any way to do timing analysis? Setup time is when the input data is stable before the clk signal. So can i manually change when i want my input signal to be high. Do i mention it in the test bench or how??? Other than like design and simulation can anyone also pls mention what are the other important aspects to be learnt in digital design. Like i read something about placement too. If anyone can kindly let me know the steps for timing analysis would be really helpful!!!! Thank you!!!