Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Psub _ StampErrorFloat

Status
Not open for further replies.

sohaee

Junior Member level 2
Joined
May 28, 2016
Messages
20
Helped
1
Reputation
2
Reaction score
1
Trophy points
3
Activity points
153
Hi there!

I encounter these errors while running LVS in cadence:
Psub_term_StampErrorFloat
Psub_StampErrorFloat

I'm using deep Nwell, and this DNW is surrounded by Nwell. the Nwell is connected to VDD by M1_Nwell contacts and the bulk of all NMOS transistors is connected to the ground. (there is no PMOS)

does anyone know what is this error for?
 

Psub_term_StampErrorFloat
Psub_StampErrorFloat

I'm using deep Nwell, and this DNW is surrounded by Nwell. the Nwell is connected to VDD by M1_Nwell contacts and the bulk of all NMOS transistors is connected to the ground. (there is no PMOS)

NMOS p-bulk connected to ground by metal?
P-substrate contacts connected to ground by metal?
 
  • Like
Reactions: sohaee

    sohaee

    Points: 2
    Helpful Answer Positive Rating
thank you so much for answering!:)

NMOS bulk is connected to ground by metal, but substrate not. the whole circuit is in the DNW and all NMOS transistors bulk is connected to ground. you mean I should add extra contacts and connect some place out of the DNW to the ground?
but I don't want anything out of the DNW...
 

Rules have no idea what you want. They express what the
foundry wants, which is in this case an explicit ohmic (and
not very many ohms) tie of every electrically distinct "well"
(N or P) to a known signal (usually, but not necessarily, a
supply pin). This is all to prevent the foundry to have to
spend time and effort dealing with customer panics that
have to do with floating FET bodies causing mystery FU.

It's not about what you may want out the the NWell.
It's about making sure that whatever goes on there, is
on purpose.

In the rules logic a same-species contact to the well
(perhaps additionally constrained as to max distance
from active) "stamps" that region and "unstamped" are
declared an error.
 
  • Like
Reactions: sohaee

    sohaee

    Points: 2
    Helpful Answer Positive Rating
So you mean I must connect the Psub out of the well to the gnd?
I did it, and there is no error anymore!:) Though I had to make it a bit larger; it seems it's critical for the circuit to be fabricated correctly.(I concluded from what you and erikl said,I hope I'm right:D)

Thank you so much for your very kind help!:)
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top