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    CTS question about create_clock

    There are two clock made constraint as create_clock.
    If I don't set false_path about these two clock.
    After CTS, are these two path balance ?
    What action does CTS handle false_path constraint ?
    For CTS, these two clocks are treat as independent and have not balance ??
    Thanks.

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    Re: CTS question about create_clock

    Which tool set do you use ?

    For Synopsys ICC, 2 primary clocks ( created by create_clock command ) are not balanced in their latencies or say, they are indenpendent in latency.
    The same CTS for the case of 2 clocks which have false path relationship.



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    Re: CTS question about create_clock

    Quote Originally Posted by nemolee View Post
    There are two clock made constraint as create_clock.
    If I don't set false_path about these two clock.
    After CTS, are these two path balance ?
    What action does CTS handle false_path constraint ?
    For CTS, these two clocks are treat as independent and have not balance ??
    Thanks.
    I think what you are asking is if you can assume any relationship between independent clocks. The answer for that is no. But I am not sure I understood your question, really convoluted English there.



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    Re: CTS question about create_clock

    This is only conjecture...

    Maybe the situation is two synchronous clocks (created externally) are coming into their ASIC and they want them to be usable as synchronous clocks internal to the ASIC, therefore they want the clock trees to be balanced.



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    Re: CTS question about create_clock

    My senior colleague in company replied me.
    False path is just timing constraint, not effect CTS and won’t be see.
    CTS is just balance leaf pins of its create clock.
    Each “create_clock” won’t balance to each “create_clock”.
    Eg. A clock may 1ns latency.
    B clock may 5ns latency.



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  6. #6
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    Re: CTS question about create_clock

    Quote Originally Posted by nemolee View Post
    My senior colleague in company replied me.
    False path is just timing constraint, not effect CTS and won’t be see.
    CTS is just balance leaf pins of its create clock.
    Each “create_clock” won’t balance to each “create_clock”.
    Eg. A clock may 1ns latency.
    B clock may 5ns latency.
    wrong. false path affects the CTS if it isn't set properly. remember that CTS tries to balance skew, and might waste resources to balance the two flops in this false path if it happens to be a critical path.



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    Re: CTS question about create_clock

    false_path constraint won't be affected in CTS interclock balance.

    And ICC doesn't adjust interclock skew balance by default.
    In icc, You would be set another commands.

    "set_inter_clock_delay_options -balance_group "$need_to_balance_clocks" -balance_group_name balance_grp1 -target_delay_clock $longest_delay_clock

    and perform shown below in mega command.

    "clock_opt -inter_clock_balance"



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    Re: CTS question about create_clock

    Quote Originally Posted by hyun5226 View Post
    false_path constraint won't be affected in CTS interclock balance.
    This is not correct.

    You are assuming CTS targets skew only. it doesn't. not anymore.

    Think of CTS as a retiming engine. It needs proper false paths to be defined.



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