Basic concept of Transceiver in FPGA

Hi,

I would like to know basic concept of transceiver which implemented in FPGA.

What is it actually? Some Internet source say it is just Serializer/Deserializer for I/O for high data rate(range of gigabit) transmission. Some say it is PCS + PMA. I think I have not really understood it. can anybody please expalin it little bit?

What is its use?

What are the basic steps that need to be followed to implement it in FPGA?

sorry if my question is so obvious.

Best Regards

beginner_EDA said:

What is it actually? Some Internet source say it is just Serializer/Deserializer for I/O for high data rate(range of gigabit) transmission. Some say it is PCS + PMA. I think I have not really understood it. can anybody please expalin it little bit?

What is its use?

What are the basic steps that need to be followed to implement it in FPGA?

Click to expand...

The terminology gets blurred by many web sites and that is probably causing the majority of your problems with understanding this topic.

You should read the documents provided by say Xilinx or Altera on their transceiver implementations. The multi-gigabit transceivers that perform clock recovery and extract data from a serial input of 8b10b or 64b66b encoded symbols. All of this is done in a hard IP block that uses current mode logic (CML) with both the analog and digital components implemented in the IP.

The Serializer/Deserializer stuff you may have seen might be referring to the Xilinx SelectIO ISERDES/OSERDES blocks that perform various ratios of serial to parallel conversions in user I/O pins. This only defines the serial/parallel conversion logic and doesn't have any inherent encoding or clock recovery support. All of that stuff would have to be implemented in the FPGA fabric. This SerDes is entirely different than the transceivers and can use any of the user I/O voltage standards.