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spi (serial peripheral interface) modeling and verification

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pradeep007

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spi(serial peripheral interface) modelling and verification

please help me to write testbench for the spi(serial peripheral interface) verilog code.please go through the attachments for the problem statement and the verilog code .


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module spi(clk, csz, MISO,MOSI);
input clk, csz, MOSI ;
output MISO ;
wire MOSI;
reg MISO ;
reg [6:0] address;
reg [7:0] memory [0:127];
reg [7:0] data;
reg rw;
reg [3:0] i=0;
reg [2:0] j=0,k=0,l=0;
integer m,n;
initial
begin 
for (m=0;m<128;m=m+1)
begin 
    
        
         memory[m]=8'b0;\\initialise memory to zero
    
end
 
end
always@(posedge (clk))begin
   
        if(csz==0)begin
     
      if(i<=7)begin
            address[k] <= MOSI;
            k=k+1;
      end
      if(i==7)begin
            rw <= MOSI;
      end
      if (i>=8)begin 
            if ((rw==1))begin
                    memory[address][j] <= MOSI;
                    data[j] <= MOSI;
                    j=j+1;
            end
            else begin
                 MISO <= memory[address][l];
                 data[l] <= memory[address][l] ;
                l=l+1;   
            end
            
        end
          assign i=i+1;\\counter which keeps track of clock for read and write operation
     end
      else begin
      data <= 8'b0 ;
      address <= 8'b0 ;
      i<=4'b0 ;
      j<=3'b0 ;
      k<=3'b0 ;
      l<=3'b0 ;
      rw<=1'bx;
      end
        
     
end
        
endmodule

 

Attachments

  • spi_problem_statement.pdf
    2.8 MB · Views: 115

Re: spi(serial peripheral interface) modelling and verification

What problems are you having?
 

Re: spi(serial peripheral interface) modelling and verification

What problems are you having?
The problem is you didn't write the testbench for them like they wanted. :roll: :wink:

OP, try looking at this site http://www.testbench.in/. Personally I'm not all that impressed by that site but at least it gives you a place to start and allows you an opportunity to actually learn something instead of having it given to you.
 

Re: spi(serial peripheral interface) modelling and verification

Hi tricky..,
I have written testbench(tb) for the spi code and i simulated the tb but the problems are:-
1) the memory is not linked to output pin (miso) ,this leads to failure of read operation.
2)when i declare csz=1 in tb, the rw,i,j register do not reset.
 

Re: spi(serial peripheral interface) modelling and verification

Hi tricky..,
I have written testbench(tb) for the spi code and i simulated the tb but the problems are:-
1) the memory is not linked to output pin (miso) ,this leads to failure of read operation.
2)when i declare csz=1 in tb, the rw,i,j register do not reset.

You didn't connect something up in the testbench, or you didn't follow the correct protocol, or you didn't follow the slaves address map, or something else is wrong.

One observation is you're code is badly written, it's written as if Verilog is a procedural language like C. This code doesn't describe hardware it's a program (with an assignment statement assign i=i+1; inside a always block, SYNTAX ERROR). You should read a Verilog book or at least a tutorial on how to write Verilog code for synthesis as it's obvious that you don't know the language well enough to write code.
 

Re: spi(serial peripheral interface) modelling and verification

You didn't connect something up in the testbench, or you didn't follow the correct protocol, or you didn't follow the slaves address map, or something else is wrong.

One observation is you're code is badly written, it's written as if Verilog is a procedural language like C. This code doesn't describe hardware it's a program (with an assignment statement assign i=i+1; inside a always block, SYNTAX ERROR). You should read a Verilog book or at least a tutorial on how to write Verilog code for synthesis as it's obvious that you don't know the language well enough to write code.

will u help me by correcting the code? ,may be i can learn something from you.:)
 

Re: spi(serial peripheral interface) modelling and verification

I'm not a teacher, I'll help with specific problems that I can spot in 5-10 min but I don't have the time to devote to instructing someone on how to code. There are tutorials http://www.asic-world.com/verilog/veritut.html, http://www.ece.umd.edu/class/enee359a/verilog_tutorial.pdf, http://www.referencedesigner.com/tutorials/verilog/verilog_01.php, etc., that you can read to help you learn how to code in Verilog.

Beyond that I can mention things like:
  • read up on blocking and nonblocking assignments in Verilog, http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf
  • comment code....comment code...comment code...comment code...
    basically add comments to your code that don't just state the obvious e.g.
    Code:
    a <= a + 1; // add one (uh that's kind of obvious)
    a <= a + 1; // increment for next address (uh, not much better)
    a <= a + 1; // obtain next address to access the next column entry of the array (gives the why)
  • Improve the formatting of your code, be consistent in the spacing (and no tabs) for each level of if, case, etc. use black lines to group code.
 

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