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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 library ieee; use ieee.std_logic_1164.all; use ieee.fixed_pkg.all; entity str_test is end entity str_test; architecture test of str_test is begin process variable a : sfixed(3 downto -4) := b"1101_1100"; begin report "literal is " & to_string(a); report "real is " & real'image(to_real(a)); wait; end process; end architecture test;
# ** Note: literal is 1101.1100
# Time: 0 ps Iteration: 0 Instance: /str_test
# ** Note: real is -2.250000e+000
# Time: 0 ps Iteration: 0 Instance: /str_test
I want to write the values(sfixed ) in text file
but how it will be saved in my system.... in which format. I want the output values in text file. so that i can reconstruct it in MATLAB
using TEXTIO you store it as a text file. How you format it is up to you (by how you write your code).
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 library ieee; use ieee.std_logic_1164.all; use ieee.fixed_pkg.all; entity str_test is end entity str_test; architecture test of str_test is begin process file f : text open write_mode is "some_file.txt"; variable l : line; variable a : sfixed(3 downto -4) := b"1101_1100"; begin write(l, "literal is " & to_string(a) & lf); write(l, "real is " & real'image(to_real(a)) ); writeline(f, l); wait; end process; end architecture test;