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How to characterize the CARRY4 primitive in Virtex-5 FPGA

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msdarvishi

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Hello everyone,

I am using CARRY4 primitive as delay line in my design and now I would like to characterize my design to evaluate the effect of temperature, jitter, etc. on the behavior of CARRY4 primitive and calculate and plot the DNL and INL curves. I do not know how to come and start with the characteriazation?! I know that I have to perform PVT (Process, Voltage, Temperature) analysis but can I see its results in simulations? Is it possible to characterize the design with simulation?
Any kind helps, hints and links toward the characterization on delay line are in advance appreciated.

Regards,
 

I don't see how you are going to do this as there is no way to extract the actual design (as say a spice deck) of the "ASIC" (full custom silicon) that Xilinx produces. So the only way to characterize anything is to build a design that tests the path you are interested in on thousands of the parts in all corners.

The biggest question I have is WHY are you doing this? What reason is there to attempt to characterize something Xilinx has already done to create the timing files for the FPGA (and has updated as they refine the manufacturing process of the die).
 

ads-ee said:
I don't see how you are going to do this as there is no way to extract the actual design (as say a spice deck) of the "ASIC" (full custom silicon) that Xilinx produces. So the only way to characterize anything is to build a design that tests the path you are interested in on thousands of the parts in all corners.

The biggest question I have is WHY are you doing this? What reason is there to attempt to characterize something Xilinx has already done to create the timing files for the FPGA (and has updated as they refine the manufacturing process of the die).
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Dear @ads-ee,

Thanks for your reply. Regarding your question, I used CARRY4 primitive in my design as a delay line and I would like to know what is the effect of temperature on the accuracy of that? Or, what is the effect of jitter and other parameters on that? So, I have to characterize it. I am looking forward finding a way to characterize the CARRY4 primitive in all corners, but HOW??

I would cordially appreciate if you could give me a hint to proceed.

Thanks,
 

I've never done any work in the area of characterizing ASICs so I have no clue how you would go about that.

All I know is from what I've been told by the FAE that came directly from the factory. The worst case range of timing values for something is:
best case delay: 10% of the worst case timing value of the fastest speed grade
worst case dealy: the worst case timing value of the slowest speed grade part

For some reason that I don't recall why I required the best case expected delay (Best P, High V, low T) which isn't published in any of the documentation so had to find out what the expected value would be. I do remember it was for fixing some design flaw that I inherited from an employee that was laid off.
 

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