Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

CMOS Transistor size ratio

Status
Not open for further replies.

qasimq1@gmail.com

Newbie level 1
Joined
Aug 26, 2013
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
9
please share the parameters for 90 nm cmos process

drain current,small signal parameter and intrinsic gate capacitance parameters for 90 nm cmos process (T=300k)
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top