Generating a pulse with 1ns pulse duration in fpga

Hi dear all
I wanna generate a pulse (1ns duration) in fpga but i am not sure that it is possible because max clock frequency of fpga ( virtex family) is 200MHz . Now please guide me that is it possible to increase max clock freq of fpga by DCM to acchive 1GHz?

vahidsh said:

Hi dear all
...max clock frequency of fpga ( virtex family) is 200MHz?

Click to expand...

This is not a correct statement.
max clock frequency of a design implemeted on FPGA depends to FPGA family, speed grade, routing, design and ....
plz Refer to datasheet for some more information about FPGAs max clock.

Why you need 1ns pulse duration? where you need this? in an IO port or inside FPGA.

FPGAS supporting 500 MHZ core clock can generate 1 ns pulses using DDR output registers.

FvM said:

FPGAS supporting 500 MHZ core clock can generate 1 ns pulses using DDR output registers.

Click to expand...

You can also do this internally using opposite edge flip-flop outputs and an AND gate, though the intentions is likely what FvM thinks they need this pulse external to the FPGA.

Now the FPGA the OP may be using if it's really Virtex and not Virtex-7 then the 200 MHz is likely the maximum frequency period, if they need 1 ns pulse then use the technique above and a DCM to generate 5 phases of the clock and have each phase generate a phase shifted pulse and AND them all together to generate an approximately 1 ns pulse. It's likely this would require hand placement of all the FFs and possibly directed routing to lock everything down so it will meet timing as the source pulse will have some pretty tight timing. This still might not even work as the maximum toggle rate in Virtex isn't even close to 1GHz (if I recall correctly).

Thank you for your answer,
Really i want to design Pulse Generator(high voltage in order of Kilo volt). The PULSE WIDTH of pulse Generator should be in orders of 1-2 nano second and the Rise time and fall time should be less than 1 second. The repetition of these pulse should be in order of KHz.
Now i wanna just make these pulse to excite one another circuit (amplify voltage from 1v to 10 kilo volt).
And i know that the internal signals of FPGA could not be used as external signals.
So i wanna know that What the minimum width of pulse ( external signals of fpga ) is ? nano second or microsecond ?

-merged-
Thank you.
But i meant about external signals of FPGA not internal.

-merged-
Thank you dear ADS_ee,
what about the maximum speed of external signals of fpga?

The PULSE WIDTH of pulse Generator should be in orders of 1-2 nano second and the Rise time and fall time should be less than 1 second.

Click to expand...

Presume you don't mean 1 second here.

Generally, the FPGA will output digital pulses, rise/fall-time is a matter of the external high voltage circuit.

"Amplifying" nanosecond pulses to kV or even 10 kV level is much more challenging than basic FPGA pulse generation, but should be discussed separately in the Analog Circuit Design section, it has nothing to do with FPGA design.

We already confirmed that it's feasible to generate nanosecond pulse widths with recent FPGA. For an exact calculation you should mention the chosen FPGA type respectively the intended type range.

Yes i meant 1 nanosecond( rise/fall) time not 1 second.
Thank you again. Now based on your guide, i am sure that the pulse 1ns rise/duration/fall ( as an exciter for an circuits with amplitude about 1 volt) is a possible task.

Rise/fall-time of FPGA outputs is typically below 500 ps, depending on the IO standard and programmed drive strength. In so far rise/fall-time is no problem. For the smallest pulse width you have to refer to the FPGA core clock frequency and PLL specifications. Below the resolution of 1/2 clock period (using DDR output registers) there are also options to combine multiple phase shifted clocks or use additional gate delays.

Thank you dear FvM
Another question:
Is it possible to generate a pulse (by fpga ) with different rise time as an external signal? Rise time is about 4-10 nano second.
For example fpga generate some pulse with 4 nano second rise time and then chenge the rise time to 6 or 8 nano second?

That's not possible with digital FPGA outputs.

You could use a very fast DAC (e.g. 1 GS/s speed) generating a staircase signal and an interpolating filter. Or an analog signal generator with programmable ramps.

But making the rise time of a kV signal programmable is much more difficult. Typically switched LC or RC networks would be used.