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VGA Signal 1280 x 1024 @ 75 Hz at slow rate

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bilal_oct

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The monitor which I have accept the signal 1280 x 1024 @ 75 Hz which need pixel clock 135 MHz.

http://tinyvga.com/vga-timing/1280x1024@75Hz

Is it possible to drive the VGA Signal for the monitor mentioned above from the FPGA at slow rate like 30 frames per second ? In this case what will be the pixel clock for 30 frame per second ?
 

Hi,

It depends on the monitor.
We don't know it's name, type, manufacturer.

So it's on you to read it's manual.

Read about "interlaced" mode.

Klaus
 

@ KlausST

The monitor is DELL 1905 FP
 

The quoted pixel clock is only if you want to run absolute maximum resolution.
In this case 1280 x 1024 or to display well over a million pixels on the screen.

Is it possible to drive the VGA Signal for the monitor mentioned above from the FPGA at slow rate like 30 frames per second ? In this case what will be the pixel clock for 30 frame per second ?

No, the standard in this case says 75Hz and that absolutely must be your vertical sync rate.

First thing you must do is generate the EXACT line scan frequency of 64 Khz from a crystal, then divide down the EXACT 75.0 Hz frame scan frequency from line scan frequency.

That will get your monitor scanning with 1024 visible lines and a 74 Hz frame rate.

Now you do not need to run the full 1280 pixels per line.
You can run a pixel rate at a much lower sub multiple.
In my own video generator I wanted only to display 30 vertical bar graphs, so I ran a horizontal pixel rate of only 64 ! That gave me 32 vertical bars with 32 blank spaces between.

My required pixel clock to do that was only 10.24 Mhz.

The screen refresh rate must be 75 Hz, but the data going into the dual; port video ram can be refreshed at a much slower rate than that.

Here is a schematic of my own VGA timing generator.

SVGAtiming.jpg
 

@Warpspeed, the refresh rate of 75 Hz means that there should be a v_sync pulse 75 times per second but what should be the duration of each pulse ? Seconldy I could not understand 64 Khz horizontal line frequency. I guess this is the frequency of the h_sync pulse within the frame but again what about the duration of high and low h_sync. You already know that I have DELL 1905 FP which accept VGA Signal 1280 x 1024 @ 75 Hz.

My task is also to display three to five vertical bars in different colors on the monitor. The VGA signal has to be generated from FPGA after the timing requirement is known.
 

Here is your answer:
Horizontal frequency 80 Khz, horizontal sync 1uS
Vertical frequency 75Hz vertical sync 37.5uS

Don't worry too much about the sync pulse widths, my standard specifies 1uS horizontal synch, but I used 0.5uS and it worked fine.
Vertical sync for my standard says 124uS or six lines, which is what I programmed into my EPROM.
The Dell only sees sync edges, not pulse widths.
I am using a Dell E176FPb which is a 17 inch LCD monitor.

The only reason I picked the standard that I did, was the frequency division is simple, and I already had a suitable crystal.

You will need to divide down from your crystal to exactly 80 Khz.
Then divide down the 80Khz by exactly 1066 to 75 Hz.

The shematic in post #4 should work as drawn, with a 12.8 Mhz crystal instead of the 10.24 Mhz crystal that I used.

U9 just counts lines.
For my requirement I wanted some horizontal graticule lines (in various colours) for my vertical bar graphs.
The EPROM U8 just turns the RGB on and off on the desired lines, it also generates vertical sync, vertical blanking, and resets the counter U9 after 1066 lines via the cross coupled flip flop U10.

You just program the EPROM to do various things at the desired line count (0 to 1066).

Output of U1 (Q3) will be at line rate, but the other outputs will be at multiples of line rate, which produces various numbers of vertical bars. You could decode that to give timings for any number of horizontal screen divisions.
 
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