The extraordinary delay in the output of a Core generated with Coregen Xilinx ISE

Extraordinary delay in output of a Core generated with Coregen Xilinx ISE

Hi,
I know similar issues have already been discussed here, but my problem is little bit different.
I generated several cores using Coregen utility in ISE(14.7), but when ever I simulated them output appears with too much delay. In most of the cases it is more than 110 ns(which is unacceptable, please see the picture attached for a recent one). I am using verilog as project language. This time I generated a floating point maths core and instatiated in a test module to see the input and output behaiviour. Similar things happend when I generated a DCM core, and output appeared after same 115ns. Please note that I am using timescale as 1ns/1ps. I have also posted the same on Xilinx forums but no body has yet responded.
Can any body please clarify what is going on wrong on my side.

Regards

Re: Extraordinary delay in output of a Core generated with Coregen Xilinx ISE

A lack of information isn't going to help getting an answer, things like the core used and the setting used are likely important.

I'm also going to ignore your problem and let someone on Xilinx's forum answer this question. I really don't like answering questions that are cross posted on various forums as this just wastes someones time answering something that may have already been answered elsewhere. This shows a lack of respect and consideration for others volunteering their time.

Re: Extraordinary delay in output of a Core generated with Coregen Xilinx ISE

you are showing the results from the start of time at t=0. most practical designs will either make inputs as valid some time after a reset, or will ignore some number of samples after reset.

It isn't clear to me if this is just a testbench issue (eg, cores held in reset for 100 ns), an issue at startup (internal resets that take 100 ns), a lack of understanding of bandwidth vs latency (multiple-cycles to get a result), or an actual delay (modeling a combinatorial delay for a core that is actually slow).

My guess is a combination of a reset that lasts ~100ns and addition of maybe 7-8 cycles of latency in addition to a clock that starts low. (the latter is only there to explain 115ns vs 114ns or 116ns)

Re: Extraordinary delay in output of a Core generated with Coregen Xilinx ISE

You nailed it down, thanks. In fact it was indeed startup reset of 100 ns.
Thanks alot vGoodtimes.

Re: Extraordinary delay in output of a Core generated with Coregen Xilinx ISE

@vGoodtimes, you must be clairvoyant as the simulation waveform shows time starting from approximately 108.5 ns. I have no idea how you guessed that there was a 100 ns reset!

You must have gotten lucky, the OP didn't provide enough information to come to your conclusion. (and now they will think they did :thumbsdown

Re: Extraordinary delay in output of a Core generated with Coregen Xilinx ISE

@ads_ee:
There is a very good chance that a reset is involved in any early issues in a sim.

I think my default reset time in a simulation is something like 100ns and then I copy that part of the code to every testbench I write. I expected 100ns to be more likely than 112ns. 100 is a nice round number that you copy and paste and forget about. 112 is a specific number that you don't forget about and thus never ask the question.