Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

UCF for spi in nexys3

Status
Not open for further replies.
sry guys forget about the data from pc to pc..

now how can i send data from master fpga to slave fpga .. what i mean is the master sends data slave catch .. slave send data master catch.. i assigned the mosi miso sck ss for the fpga and the slave fpga in pmod connector .. what should i do next?
 

I think it would be better to open a new thread and provide all relevant information and problems you have faced (even if you need to re-post all codes, block-diagrams, UCFs,etc). Then ask the question. This already #42 and has gone messy.
 

The OP has stated an intent to start a new thread, with code, ucf, block diagram, and a specific coherent question, therefore this thread has been locked by a moderator and no further replies are allowed.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top