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  1. #1
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    full bridge spikes problem

    I am designing a DC/DC converter.
    I chose the fullbridge topology. The requirements are as follows:
    Vin = 75 - 125 Vdc Vout = 200V P = 600W Fs = 100 Khz

    the basic schematic is as follows DC/DC schematic
    Click image for larger version. 

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    I use ZVS for soft switching. the problem is the big spike in the Vds on the MOSFETS Vds M2 and M4.

    Click image for larger version. 

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    The image above shows the Vds on the down MOSfets and the Vgs for all mosfets. the signal A is the up - left mosfet the signal B is up - right mosfet the signal C is down - left mosfet and the signal D is down - right mosfet

    I see that the voltage spike is generated in right leg transition (when D switch is falling)
    The same spikes occurs on the primary current I don't know why occurs.
    Click image for larger version. 

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    I dont know if the problem is in primary or secondary?.
    I provide a large time for discharge the parasitics capacitances (over 400 ns).
    Which components oscillate in my design for generate this spikes?
    regards and thanks for the answers.

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  2. #2
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    Re: full bridge spikes problem

    Your fets not good for Phase shift full bridge (PSFB). They have much Cds capacitance, and also, the internal diode is relatively slow…and you make this worse by paralleling them…..so there are two to reverse recover….and also…..you use two, so there is even less I(FET)*Rdson voltage to reverse recover the intrinsic diodes with.
    For PSFB, you must use FETs which are specifically for PSFB useage, eg by infineon or st.com or Fairchild etc….paralleling is not really a good idea for PSFB.

    IRF540 datasheet
    http://www.vishay.com/docs/91021/91021.pdf

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    The below references tell you the true horrors(!!!) of FET failure in the PSFB…this is why you must only use FETs which specifically are for PSFB…and they will have a low trr diode in them, and also they tell you the Cds value you have to use to do the calculation with so as to ensure ZVS. (or rather, the datasheet tells you , i meant to say)

    https://www.fairchildsemi.com/applic...AN/AN-7536.pdf

    http://www.microsemi.com/document-po...r-applications

    http://www.st.com/st-web-ui/static/a...CD00171347.pdf

    http://www.infineon.com/dgdl/s30p5.p...535748559c3fcd

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    Also, you have no diode snubbers
    Your diode is nice and fast, but you can get faster still, why dont you?
    STTH30R06 datasheet:
    http://www2.st.com/content/ccc/resou...CD00045268.pdf

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    Also, i dont think that 100R should be across the secondary

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    Also, i think you should use a sim transformer without the ideal transformer "thing" and just put the Lp and Ls values in there to correspond to the turns ratio.

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    Also, i think you should use a sim transformer without the ideal transformer "thing" and just put the Lp and Ls values in there to correspond to the turns ratio. Anyway, regarding the scope shot, did you use a probe with a dangling ground lead, ...just use a bit of coax, because the ringing looks like probe noise......unhook the probe and short the ground clip to tip and see if you still see the ringing...if so, then its "pickup"..which it probably is.

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    you see this fet, it tells you the effective output capacitance of the fet cds, "TIME related", and this is the value that you use to calculate your dead time in your PSFB
    Coolmos fet for PSFB
    http://www.infineon.com/dgdl/Infineo...2e14e6178c6e0a

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    Notice also how the coolmos fet has a large gate charge figure.......this is good because a slow switch on of a PSFB FET reduces instances of "latchup" in the PSFB FET...and you can get a slow switch on easier with a high Qg



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  3. #3
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    Re: full bridge spikes problem

    Hello Treez thanks for the answer
    I use this MOSFETS because are really inexpensive and easy get in my country.
    I am aware the COSS for this mosfets is big and the trr of the body diode is slow. but I compensate with big time for left leg and right leg transition, for give time to recompose of body diode. this is not suficient for solving the problem? the problem would be solved by placing a external diodes with less trr?

    The resistor of 100R is a resistor that I put in the prototyope. when using a resistance is that point, the signals are better.



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  4. #4
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    Re: full bridge spikes problem

    Yes…..less trr FET needed. Infineon do them, and others.
    Having a long dead time is not going to stop the destructive latchup that I speak of, and the above articles tells of this horror also….having a long dead time makes no difference to your chance of it happening…..in light load….there is not enough I(FET)*Rdson voltage to recover the diodes properly, then when they eventually get reverse biased…..severe reverse recovery flows and turns on the parasitic bjt.

    If you are going to use those IRF540’s , then you better off not doing a PSFB.

    PSFB is known to be much worse than LLC for exposing the FETs to the horrors of reverse recovery and latchup

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    you should use RC snubbers across the diodes, and the 100r , if anything, should be a RC instead. Also, often with PSFB a regenerative secondary side snubber is needed.

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    .................................................. .................................................. ...................
    https://www.edaboard.com/thread342663.html
    …this thread discusses PSFB (phase shift full bridge) converter. It explains how the standard PSFB does nothing to decrease turn-off switching loss compared to the plain full bridge. –Only if you use the “modified PSFB”, which has extra capacitors across the primary side FETs does it soft switch the primary fets. –But this then has other ramifications.
    Also, the thread failed to really defend the plain PSFB, even saying that the “modified PSFB” should again be modified by adding freewheeling diodes to the primary side rails….but this brings yet more ramifications.

    The “evil”, noisy Plain full bridge isn’t as noisy as first thought……the leakage inductance in the transformer actually diminishes overlap switching losses in the primary side FETs at turn-on. The leakage also means that the dv/dt and the di/dt with the secondary diodes is much less than otherwise. Also, a plain full bridge never needs a secondary side regenerative snubber. –And special FETs with low trr diodes in them are not needed for a plain full bridge converter.



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