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IC Compiler Read_sdc timing constraint has error " cant find VDDG'

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tridoan

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Hi all,

I have a problem with IC Compiler at read_sdc timing constraint (DC compiler and other steps had no error):


ICC_Read-sdc-error.jpg

Please help me if you had the same error before. How can I fix it?

Thanks,

TriDoan
 

It doesn't look like the problem comes from the SDC at all, but instead from the library view. You should use consistent views that have the same power pins. Most likely your netlist has no power pins.
 

ThisIsNotSam said:
It doesn't look like the problem comes from the SDC at all, but instead from the library view. You should use consistent views that have the same power pins. Most likely your netlist has no power pins.
Click to expand...

Thanks for your reply !!!

The design verilog was tested with direct techbench, everything looked good. Then, I applied to DC Compiler: everything looked good too, timing was met.. IC Compiler was running very good: read gate level code okei, but when it came to read-sdc: the error popped up. I dont know where the problem came from, and how can I fix it. If you have any ideas, please share..Thanks !!!
 

did you check the power pins? your verilog netlist should look like this:

Code: 
AND2 myand (VDD, GND, A, B, Y)

instead of like this

Code: 
AND2 myand (A,B,Y)
 

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