[SOLVED] PEIE in PIC 16f877a and its relation with TMR0

hello

I am explaining TMR0 to some students, and I followed the explanation in datasheet. The datasheet says that the pin PEIE (Peripheral interrupt enable) has a relation with TMR0.

but this is wrong. I tried to put PEIE = 0 and this did not stop TMR0 from enabling its interrupt.

if this is in datasheet, why PEIE has no effect?
the other question, what is the usage of PEIE? TMR0 is not considered as one of peripherals ? what are the peripherals then?


thanks

Which data sheet are you looking at?
Looking at https://ww1.microchip.com/downloads/en/DeviceDoc/39582C.pdf Section 2.2.2.3 on page 24, it shows the INTCON register that contains a number of control bits including PEIE (the peripheral interupt enable) and the TMR0IE which enables the Timer0 interrupt (as well as TMR0IF and other bits). However I would not say that this shows that there is a relation between them.
If you look at Figure 14-10 on page 153, you will see that PEIE does not control the TMR0IE/TMR0IF 'and' gate.
The same figure will show you the answer to the questions in your last paragraph.
Susan

The 16F877A and most other 16F devices split the interupts into two categories, the 'core' interrupts from TMR0, the external interrupt pin and the IOC detector, and the 'peripheral' interupts from all other sources. PEIE is the enable/disable bit for the peripheral sources but TMR0 is not in that group so it will not have any effect on its ability to generate interrupts.

As Susan explains, if you look a the tree diagram 14.10 "interrupt logic" in the data sheet, you will see how the different interrupts and their enable bits work together.

Brian.

Aussie Susan said:

Which data sheet are you looking at?
Looking at https://ww1.microchip.com/downloads/en/DeviceDoc/39582C.pdf Section 2.2.2.3 on page 24, it shows the INTCON register that contains a number of control bits including PEIE (the peripheral interupt enable) and the TMR0IE which enables the Timer0 interrupt (as well as TMR0IF and other bits). However I would not say that this shows that there is a relation between them.
If you look at Figure 14-10 on page 153, you will see that PEIE does not control the TMR0IE/TMR0IF 'and' gate.
The same figure will show you the answer to the questions in your last paragraph.
Susan

Click to expand...

please look at the page 55 in the same datasheet that you sent. In page 55 , it shows the bits in INTCON that associated with TMR0, and surprisingly PEIE is one of them, even if this pin does not appear in block diagram of TMR0 as you said.

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betwixt said:

The 16F877A and most other 16F devices split the interupts into two categories, the 'core' interrupts from TMR0, the external interrupt pin and the IOC detector, and the 'peripheral' interupts from all other sources.
Brian.

Click to expand...

then, TMR1 and TMR2 are considered peripehral interrupts? or are dealt as TMR0 as core interrupt?
also, what made TMR0 special? And where did they say this in datasheet?

please look at the page 55 in the same datasheet that you sent. In page 55 , it shows the bits in INTCON that associated with TMR0, and surprisingly PEIE is one of them, even if this pin does not appear in block diagram of TMR0 as you said.

Click to expand...

I think that's an error in the data sheet, the PEIE should be shaded. The IC is about 15 years old now so maybe Microchip are not applying corrections to old data sheets.

then, TMR1 and TMR2 are considered peripehral interrupts? or are dealt as TMR0 as core interrupt?
also, what made TMR0 special? And where did they say this in datasheet?

Click to expand...

I suspect that is for historical reasons. On older devices (that the 16F877A evolved from) there was only one timer and Microchip's policy of keeping the registers as similar as possible across the range meant they kept INTCON like it's predecessors. The addition of other timers and peripherals meant more interrupt enable bits and interrupt flags were needed and they wouldn't fit in the existing INTCON 8 bits. Sensibly, they moved them into other registers and gave them their own (PEIE) master enable bit.

Brian.